Abstract: A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing leakage or other electrical measurements between copper features on two different metal levels.

Abstract: An integrated circuit CMOS structure and method for forming the structure provides gate sidewall spacers which are independently optimized for the n-channel and p-channel devices to improve hot-carrier lifetime while maintaining high drive currents. This is accomplished by providing polysilicon spacers for the n-channel devices and silicon nitride spacers for the p-channel devices.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining.

Abstract: An improved Silicon-On-Insulator (SOI) device structure with a thin SOI silicon layer maintains excellent Ioff DC characteristics without degrading device AC speed and characteristics. The device structure comprises double gate sidewall spacers including an inner polysilicon spacer and an outer dielectric (nitride or oxide) sidewall spacer.

Abstract: An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

Abstract: An SEM measurement standard for measuring linewidths of 0.1 microns and below utilizes two different conducting materials in order to prevent charging effects. The top material is selected to use grain morphology to focus secondary electrons, and to obtain improved image contrast. The inventive standard is comprised of materials which are commonly used in semiconductor manufacturing and which do not cause contamination of fabrication facilities.

Abstract: An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

Abstract: A wet spray cleaning process for removing thick organic layers including hardened photoresist from the surface of silicon wafers yields low residual particle counts for photoresist thicknesses up to 3 microns, and maintains low residual particle density for oxide-covered wafer regions. The cleaning process uses multiple cycles of SPM/DI/APM/DI, without an intervening drying step therebetween.

Abstract: A process for, and apparatus for, Chemically-Mechanically Polishing (CMP) a semiconductor wafer with a slurry including ElectroRheological (ER) and/or MagnetoRheological (MR) fluids. The combination of the materials and an electric field provides inherent tuning of polishing rates, locally and globally, and improves flatness and uniformity, as well as minimizing recession and erosion.

Abstract: A process for growing an ultra-thin dielelctric layer for use as a MOSFET gate or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density electron traps, and impedes dopant impurity diffusion from/to the dielelctric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract: An improved tungsten plug/Local Interconnect slurry for Chemical Mechanical Polishing which does not require inclusion of a chemical stabilizer. The slurry is made using a combination of two separate batch mixings of stable ingredients and Point-of Use mixing of portions of the two batches, whereby the oxidizers are combined with the coated abrasive mixture immediately prior to dispensing the slurry onto the polishing pad by combining selected flows from each of the two batches to form a total flow rate equal to the required rate of slurry flow onto the polishing pad.

Abstract: A thin film which is substantially free of measurable surface defects due to second-phase inclusions is disclosed. The film is composed of multilayered strata of a first metal oxide interspersed with single molecular layers of a second metal oxide, where the second metal oxide is effective to absorb second-phase defects which form in the first oxide layers.

Abstract: A sputter magnetron ion source for producing an intense plasma in a cathode container which ionizes a high and substantial percentage of the sputter cathode material and means for extracting the ions of the cathode material in a beam. The ion extraction means is implemented by a magnetic field cusp configuration with a null region adjacent to the open end of the cathode container. Ions so produced are able to be directed at right angles to a substrate being coated for efficient via filling.

Abstract: An all digital data algorithmic recovery method and apparatus which operates at jitter greater than 25% and where run length is more than 1000 bits and which uses self calibrated delay elements to phase align a locally generated time ruler reference with the data average transition position to reliably establish the sampling time for retrieving data from an incoming binary sequence at the center of the data eye. The phase adjusted time ruler signal is used to sample transition positions of the data and the sampled data is statistically analyzed in a state machine wherein the time ruler is a broadband signal comprising a first and second base frequency and wherein the period of one of said frequencies is ##EQU1## where F.sub.R equals the receiver local clock frequency and F.sub.T equals the frequency of the distant clock.

Abstract: Improved methods of using an ion trap mass spectrometer, whereby AC voltages supplemental to the AC trapping voltage are used for scanning the trap, for conducting chemical ionization experiments, and for conducting MS.sup.n experiments, are shown. In one embodiment a broadband supplemental AC voltage is applied to rid the trap of ions above or below a preselected cutoff mass. This is particularly useful in conducting chemical ionization experiments for eliminating high mass sample ions that are formed when the reagent gas is ionized by electron impact ionization. Likewise, this technique may be used to eliminate low mass reagent ions when conducting an electron impact ionization experiment in the presence of a reagent gas. In another embodiment a non-resonant, low-frequency supplemental voltage is applied to the trap causing trapped ions to undergo collision induced dissociation. Multiple generations of ion fragments may be simultaneously formed in this manner, thereby enabling MS.sup.n experiments.

Abstract: All digital, high frequency data separation receiver apparatus and method for ascertaining the correct sequence of received digital data without a phase locked loop or an analogue voltage control oscillator (VCO) method, which employs a series of time delay circuits to establish time rulers to unambiguously determine the sequence of received bits.

Abstract: Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.

Abstract: A self calibrated time delay circuit including a plurality of serially connected unit delay cells each having an output tap which is selectable, a registration means for simultaneously determining the status of each output node of each of the unit delay cells, combinatorial and sequential logic units for analyzing said registration means and sending error correction commands to an up/down controller, said up down controller providing a command code for controlling the delay of each said unit delay by selecting which tap is output from said unit delay cell.

Abstract: Technique and apparatus for planarizing microsteps on a substrate by compressing the surface to be smoothed against a frozen layer of an etchant, where the compressive force is sufficient to melt the etchant at the contact edges between said microsteps and said etchant.

Abstract: A method and apparatus for improving the reliability of resynchronization in a serial frame based protocol communication system which can avoid resynchronization when line loss erroneously causes data to appear as a redundant unique code pattern. The synchronization is only initiated if two such unique code pattern bytes are received within a specified time separation.