Abstract: Dry toner removable developing cartridge of the disposable type, for electrophotographic printers, comprising a photoconductive drum, a donor sleeve contacting the photoconductive drum and partially housed in a developing tank having a stirrer for the developing material contained therein, the donor sleeve conveying to the photoconductive drum a predetermined amount of developing material, and a cylindrical reservoir, in communication with the development tank through a peripheral arc and containing radial diaphragms supported by a rotatable control shaft, which diaphragms define in the cylindrical reservoir a plurality of compartments in form of cylindrical sectors, filled with developing material, the sectors being sequentially brought into communication with the developing tank by rotation of the shaft and sequentially feeding the developing tank with developing material dropped from the compartments.

Abstract: Printer for data processing system, the printer being for installation on a working desk, and comprising a multifunctional stand having a generic handle-form member hinged to the printer body near the edge defined by the base and the rear wall, the stand being pivotable to take a non operative position close to the base or the rear wall and at least one an operative position in which the stand is positioned below and apart from the base and supports the rear portion of the printer in a position spaced apart from the working desk.

Abstract: A multiprocessor data processing system includes a system management facility which controls the loading of each control store in the respective multiprocessor. The system management facility generates a sequence of commands which puts a processor in load mode, initializes a control store address register, transfers firmware words from a main memory to the control store, resets the load mode, starts a verify operation and checks the result of the verify operation.

Abstract: An interface control circuit includes a shift register which is parallel loaded with a 17 bit binary code and with control information comprising two bits of opposite level loaded in the head cells of the register, the first bit having a control function, the second having a separation function from the 17 bit binary code. The parallel loading is performed by a load command which also sets a control flip flop and wherein a timing circuit, triggered by command, controls in continuous mode the interlocked interface dialogue as long as the control flip flop is set, and causes the register to shift its contents so as to serially unload the binary code to the interface and to serially load the register with the logic level of the control bit, until, at the completion of transferring the control bit level present at a predetermined number of register outputs is inverted, reintroduced in the first register cell and causes the control flip flop to reset and the dialogue to halt.

Abstract: A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

Abstract: A data entry terminal includes a front panel, a shroud and a base plate. The terminal may be assembled as a desk mounted unit or a wall mounted unit, depending upon the orientation of the front panel to the shroud and base plate.

Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Abstract: A communication data system is designed for resiliency by automatically replacing or bypassing defective units. The system includes a number of input/output terminals which are connected to MODEMs through a relay bank. The MODEMs send serial data to a serial I/O module which converts the serial data to bytes which it places on a VMEbus. A network processor sends the data from the VMEbus to a general purpose computer which places the data into the communications network. A general purpose computer or a back-up general purpose computer may detect a defective communication link and automatically switch to a back-up network computer, or cause a control module to switch the relay module to a spare MODEM and spare SIO. The control module may also generate a remote line test to the link between the MODEM and the terminal to determine if that link is defective.

Abstract: A host computer stores data and attribute bytes for display on a terminal or personal computer having a monochrome screen. The monochrome attributes include low intensity, underline, inverse, blink and hide. The host computer may communicate with a terminal or personal computer having a color screen without modifying the host program or the data and attribute bytes. The terminal or personal computer operator may determine the color and attribute for each of the monochrome attributes.

Abstract: A computer network system for multiple processing elements in which the multiple processing elements are coupled to a single network bus such that computer instructions from the processing elements may be transimtted simultaneously over the same network during one time interval by more than one processing element. A memory stores the instructions and a controller accepts instructions from one of the processing elements but rejects instructions from all other elements and stores and queues the rejected instructions for subsequent acceptance.

Abstract: A local area network (LAN) system is provided that is capable of accommodating a variety of computer subsystem types, and having a LAN controller which can control at substantially the same time a plurality of LANs of the same type or a plurality of different types of LANs.

Abstract: A digital computer system having a memory system organized into objects for storing data and a processor for processing data in response to instructions. An object identifier is associated with each object. The memory system responds to logical addresses for data which specify the object containing the data and the offset of the data in the object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions. Each instruction contains an operation code which belongs to one of several sets of operation codes. All instructions in a single procedure belong to a single operation code set, and associated with each procedure is an operation code set identifier specifying the operation code set to which the instructions in the procedure belongs.

Abstract: A digital computer system in which data operands are represented by names. Each procedure includes a name table, and means are provided to employ the name table to resolve the names into storage addresses at run time. The system also has the ability to run any of a plurality of S-Languages (an S-Language being conceptually similar to a machine language but of higher order); each S-Language can be optimally tailored to a high-order user language. Each procedure includes a dialect code which indicates the dialect of S-Language to which the instructions in the current procedure belong, and the system has provision to execute each procedure accordingly.

Abstract: A digital computer system having a memory for storing and providing data including instructions and a processor for processing data in response to the instructions and providing memory operation specifiers to the memory which specify an address of a data item and the memory operation to be performed on it. The instructions in the digital computer system include operation codes belonging to more than one set of operation codes and names representing items to be processed in the operation specified by the operation code. The data in memory further includes name table entries. Each name table entry corresponds to a name and contains information specifying the address of the item represented by the name. The processor includes apparatus for decoding each operation code in response to the operation code and to a dialect value contained in the decoding apparatus which specifies which operation code set the operation code being decoded belongs to.

Abstract: A digital data bus system operating asynchronously with a fixed clock and having a automatically variable data rate selected by sending and receiving units. A master clock is generated by a master controller and distributed to one or more peripheral controllers of the data bus system through a single clock line. In addition to address/data lines, a single handshake hold signal is shared by the master and all peripheral controllers. All data transfers are executed on a bus clock pulse and data transfer rate is controlled by the sending and receiving units through operation of the hold signal. A receiving unit not ready to receive information on the bus will assert hold signal on hold signal line and the transmitting unit will maintain the information presently on the bus during each clock period in of which hold signal is asserted. Data transfer is executed on next clock pulse after termination of hold signal.