Abstract: The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source and drain electrodes which are strapped to the substrate adjacent the gate insulation. The raised electrodes include interconnect portions which overlie the field oxide separating the semiconductor substrate into a plurality of active regions. The source and drain electrodes are thickest where each overlies its junction with the substrate in order to control the depth of penetration of doping impurities into the substrate. After doping the electrodes, a rapid thermal anneal is performed which diffuses the doping impurities throughout the electrodes and into thin junction regions of the substrate, immediately beneath the source and drain electrodes.

Abstract: A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level.

Abstract: A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is provided. The method prepares both the metal and non-metallic surfaces with a low energy ion etch of an inert gas through the use of an ion gun. The etching promotes the growth of copper on the metallic surface, and inhibits the growth on the non-metallic surface. Following an application of CVD copper, the surfaces are etched again to clean any residual copper from the non-metallic surface, and to again prepare the surfaces for another deposition of copper. Through repeated cycles of etching and copper deposition, the copper overlying the metallic surface is accumulated to achieve the desired thickness, while the non-metallic surface remains free of copper. A method is also provided for the selective deposition of copper on metallic surfaces to fill interconnects in damascene IC structures.

Abstract: A method is provided for a mobile station to calculate the time intervals at which it monitors cells in a cellular phone system to find the mobile station's home network in the phone system. The monitoring varies with the rate at which the mobile station reselects proximate cells to locate itself in a telephone network. The time between cell selections is used as an indication of the mobile station's mobility. The variable search intervals, determined by the time intervals at which the mobile station reselects cells, is limited to insure that the mobile station at least monitors for its home network at a minimum specified interval of time. An apparatus is also provided to initiate home network monitoring at time intervals related to rate at which cells in a cellular phone system are reselected by a mobile station.

Abstract: A system and method has been provided to selectively deliver a plurality of trigger signals to a counter/timer embedded in a microprocessor. The method provides the step of selecting a signal, from either internal or external sources, to trigger the counter/timer. If an internal source is selected, the method provides the step of selecting either a synchronous or non-synchronous signal source to trigger the counter/timer. Regardless of the source chosen, the method includes the step of generating a signal output from the selected source, and the further step of delivering the trigger signal on a dedicated connection. The method of the present invention also includes the step of counting clock cycles in response to the arrival of the trigger signal to the counter/timer. An apparatus to selectively deliver a trigger signal to a counter/timer embedded in a microprocessor from a plurality of signal sources is also provided.

Abstract: A method is provided for forming silicided source/drain electrodes in active devices wherein the electrodes have very thin junction regions. In the process silicidation material is deposited on the wafer and rapid-thermal-annealed at a temperature and for a time calculated to produce metal-rich or silicon-deficient silicide on the electrodes. The metal-rich or silicon-deficient silicide is selectively formed on the semiconductor electrodes and not on oxide or other insulating surfaces. A selective etch removes the silicidation material which has not reacted with silicon, including metal overlying insulating surfaces. Then, after cleaning the silicide surfaces, a layer of silicon is deposited over the structure and a second rapid thermal anneal is performed at a higher temperature than the first rapid thermal anneal.

Abstract: A testing and diagnostic mechanism includes an external bus master allows access of virtually all internal registers on an integrated circuit, and allows the on-chip SRAM/DRAM controllers to access external memory.

Abstract: A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed.

Abstract: A method is providing for a mobile station to vary the interval between scans by a mobile station for the beacon signals of cells in a communications system, in order to save battery power, when the mobile station is searching to select a serving cell. The method increases the interval between scans in response to the time elapsed since the start of the search. Initially, the scans are conducted with a small interval between the scans in the hope of quickly acquiring a serving cell. If a serving cell is not selected during this initial period of time, then the interval between scans is calculated to increase in response to the increase in elapsed time since the start of the search. If a serving cell is not selected during this period of calculated intervals, then the interval is set to a maximum limit to save battery power. A system for a mobile station to save power by varying the intervals between beacon signal scans when searching for a serving cell is also provided.

Abstract: A method is provided for forming multi-level profiles from a photoresist mask. The method includes exposing selected areas of a photoresist layer to two or more different patterns of light at different light dosage levels. For example, one pattern will be exposed to a relatively low dose of light, or to light for a short duration, and a second pattern will be exposed to a relatively high dose of light, or for a greater duration. The plurality of different exposures at different dosage levels occur prior to developing the photoresist. When the photoresist layer is developed, the pattern exposed to a lower dose of light will be etched substantially more slowly than the areas of the photoresist exposed to higher dose of light. By controlling the development process to completely remove the resist in the areas exposed to a high dose of light and only partially remove the resist in the areas exposed to a lower dose of light, a multi-level photoresist profile is formed.

Abstract: A method of blending water vapor with volatile Cu(hfac)TMVS (copper hexafluoroacetylacetonate trimethylvinylsilane) is provided which improves the deposition rate of Cu, without degrading the resistivity of the Cu deposited upon an integrated circuit surface. The method of the present invention uses a relatively small amount of water vapor, approximately 0.3 to 3% of the total pressure of the system in which chemical vapor deposition (CVD) Cu is applied. The method specifies the flow rates of the liquid precursor, carrier gas, and liquid water. The method also specifies the pressures of the vaporized precursor, vaporized precursor blend including carrier gas and water vapor. In addition, the temperatures of the vaporizers, chamber walls, and IC surfaces are disclosed. A Cu precursor blend is also provided comprising vaporized Cu(hfac)TMVS and water vapor. The ratio of water vapor pressure to vaporized precursor is approximately 0.5 to 5%.

Abstract: A method of forming a semi-conductor structure forming, on a prepared substrate, a ferroelectric memory (FEM) gate unit. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on a FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer, and which is formed on a conductive channel precursor.The structure of the semiconductor includes a substrate, which may be either bulk silicon or SOI-type silicon, conductive channels of first and second type formed above the substrate, an FEM gate unit formed above a channel region, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer, and wherein a conductive channel of a second type is formed under the FEM gate unit.

Abstract: The present invention provides a system and method for using the brief time intervals between cellular telephone calls on a primary cellular network to transmit and receive data over a second data-only network. The invention uses the built-in capability of the primary network to monitor and track each call and to identify the relatively short-duration intervals between each call to pinpoint when a short burst of data from the second network can be transmitted without interfering with primary network calls. The data network includes a separate telephone exchange. Selected base stations of the primary cellular network are shared with the data-only network. Land lines or other connections link the data network exchange with the shared base stations. Preferably, the data network is accessible via a public packet data network. Data calls on the second network are directed to the shared base stations and inserted into the brief intervals between primary network calls.

Abstract: A system and method of information correction using the independently derived parity of a received (n,k) cyclic digital codeword as a means for error checking so that error bursts of up to ?(n-k)-.left brkt-top.log.sub.2 n.right brkt-top.! bit positions are corrected, where n is the number of bits in the codeword and k is the number of information bits in the codeword. The method incorporates prior art techniques of burst error correction using a generating polynomial and the generation of n syndromes, in which the bit positions of potential error bits in the received codeword are identified and replaced to generate potential replacement codewords for the received codeword. The method of correcting burst errors comprises the step of classifying replacement codewords with respect to their calculated parity. The method also comprises the step of using prior art error trapping techniques to supply a replacement codeword, as the corrected received codeword, when a single replacement codeword is generated.

Abstract: A battery power supply transposition circuit has been provided to control the use of batteries in a power source supplying multiple voltages from multiple batteries that share a least one common battery. The transposition circuit includes switches to provide selective interconnections between the battery terminals which allow the order of the series connected batteries to be changed. A battery interconnection controller is also included to control interconnections between batteries, and so allow alternate batteries to be used as the at least one common battery. Changing the selection of the at least one common battery provides a means for minimizing differences in the rate at which the batteries are depleted.

Abstract: A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set.

Abstract: A voltage gradient measurement device is provided for determining the remaining lifetime of a battery used to power a radio, pager, cellular telephone, or similar device. The battery is attached to a first circuit element to obtain a history of the battery voltage which is used to determine the differential battery voltage. The battery is also attached to a second circuit element which measures the voltage margin between the battery voltage and a reference voltage representing the battery end-of-life condition. A third circuit element divides the voltage margin output of the second circuit element by the differential battery voltage output of the first circuit element to estimate the time that will elapse until the battery voltage approximately equals the reference end-of-life voltage level.

Abstract: The invention provides a technique for forming a MOS transistor with reduced leakage current and a shorter channel length between source and drain electrodes. The transistor includes a gate electrode between raised source and drain electrodes that are formed from epitaxial silicon. Typically, the raised source and drain electrodes are thin where the intersect the gate electrode so that epitaxial notches are formed between the gate sidewall insulation and the source/drain electrodes. To protect the source/drain junction areas underlying the epitaxial notches from undesired penetration of doping impurities used in the fabrication of the electrodes, the notches are covered with insulation material. In a special process step, performed between forming the epitaxial layers and implanting the layers with dopants to form source and drain electrodes, insulation material is added to the initial, relatively thin, gate sidewalls that insulate the gate electrode from the source/drain electrodes.

Abstract: A portable apparatus to test an automobile wiring harness for the location of a short in one of the wires. A transmitter is used to apply a low frequency, low duty cycle, pulsed signal to the wire under test. A receiver, with an inductive sensor, detects magnetic fields generated by the pulsed signal current flow between the transmitter and the short. The receiver generates a humanly discernable signal in response to the detected magnetic field. The operator finds the short by following the detected magnetic field of the signal pulse through the wire under test. By noting the location of a dramatic discontinuity in magnetic field strength, the operator can gauge the location of the short in the wire. The low voltage amplitude, low duty cycle, pulse signal allows the transmitter to be operated with a small battery. The low power signals also provide safety to circuits connected to the wire. The low frequency and power of the pulsed signal minimizes coupling between wires.

Abstract: A modified lead frame is provided for use with electrical component test handlers. A conventional multiple-parallel-conductor lead frame is modified to include two broad, electrically conductive shields positioned on opposite sides of the lead frame. Each shield covers a major portion of one side of the lead frame. Such lead frames are designed for mounting in a predetermined orientation on a lead frame holder, with one side facing toward, and the other side facing away from, the major mass of the holder. The conductive shield positioned on the side facing away from the holder on the modified lead frame of the present invention is electrically coupled to one or more selected conductors on the lead frame. The one or more selected conductors include the power or ground conductor which supplies power to a test component during tests. The shield which faces toward the holder is electrically isolated from all the conductors on the lead frame by an intermediate insulating layer.