Abstract: A tool with one or more chambers in a manufacturing system is identified as performing at or below an acceptable level by the following steps. Store process data from tools for each one of a plurality of individual processes for a processed object in a process database. Store tool performance data for each individual process for a processed object in a yield database. Develop statistics for similar tool sets associating data with each of the similar tool units. Generate yield numbers for each group of the similar tool units based upon the statistics. Identify poorly/well performing tool units by using the yield numbers.

Abstract: A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.

Abstract: A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Abstract: A structure with bit lines and capacitors for a semi-conductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.

Abstract: A method of forming a Flash EEPROM device with a gate electrode stack includes forming a a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about -10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 .ANG. to about 120 .ANG..

Abstract: A system provides for the easy editing of wide files for convenient viewing of selected columns, through the use of a function key that invokes a window which lists multiple possible combinations of views of the file which can be selected to present a choice of fields to be viewed simultaneously on the same screen. The fields represent a collection of columns which are a subset of the columns of the entire file. The system presents selected columns of data in a narrow width to facilitate viewing, comprehending, and/or editing the data.

Abstract: A method of output management of processing in a manufacturing plant with a plurality of stages during a running period. The method begins with the step of determining the stage In Flow of Work In Process (WIP) in the plant, determining the Out Flow of WIP in the plant, and calculating Flow Intensity of the plant, followed by calculating the equipment Capacity of the plant. The next steps are to calculate Equipment Capacity allocation of the plant, determine the bottleneck Stage Capacity of stages in the plant, determine the Rolling Output of the plant, followed by calculation of the Remaining Work In Process of the plant. Data on the Daily Output is collected. Remaining Work In Process is duplicated as Initial WIP for the next day. Testing is made to determine whether the running period has ended, and until the running period has ended, the method repeatedly loops back to the In Flow step.

Abstract: A method of manufacture of a MOSFET device with a predetermined light positive or negative doping comprises forming a first mask upon said substrate. Dopant of a predetermined positive or negative variety is implanted through the mask. A second mask is formed over the openings in the first mask. The first mask is removed. Dopant of the opposite positive or negative variety is implanted into the openings in the second mask. The process forms a pattern of positive and negative wells in the substrate, and forms a guard ring of an opposite doping variety from the wells being protected formed in the substrate.

Abstract: Fuel cell catalysts which are efficient, long-lived, and refurbishable in-situ include gold carrying a UPD deposit of another element. UPD Ag, Pt, Pd, Ir, Rh or Tl, Pb and Bi on Au crystallites are carried on and bonded to another substrate. The crystallites cause dissociative adsorption of the oxygen molecules so that four electrons are produced per molecule during the reduction reaction which is involved. In an alkaline electrolyte, the catalyst metals such as Pd, Ir, Ag, Rh and Pt show no tendency to poison the counter electrode (counter relative to the other electrode) since each of those metals is a good catalyst for both electrodes. Suitable fuels include methanol (CH.sub.3 OH), formaldehyde (HCHO), and formic acid (HCOOH).