Abstract: A polycyclic timing system and an apparatus for pipelined computer operation comprises a master state machine and a slave state machine. The master state machine produces a plurality of control signals in response to a clock signal. The master state machine comprises an oscillator, a plurality of data storage elements, and a next state feedback network. The oscillator is used to produce a clock signal that triggers the storage elements. The next state feedback network determines the control signals to output based on the current output data storage elements using logic in the next state feedback network. The slave state machine receives the control signals and uses them to produce several asynchronous pulse streams. The slave state machine preferably comprises a plurality of pulse forming state machines and a plurality of pulse transmission amplifiers.

Abstract: A Text Services Manager (TSM) maintains and uses TSM documents to ensure proper communication between applications and their needed input methods. A TSM document comprises information about the input methods and text services used by a particular instance of an application. One TSM document is preferably associated with each working document represented by an application window. Through use of the TSM document, the TSM provides for multiple instances of a particular input method, and the automatic synchronization of the input method to the active window. The preferred embodiment of the present invention comprises novel methods that provide this functionality including: methods for opening or closing a TSM aware application, methods for creating and disposing of TSM documents, and methods for activating and deactivating a TSM document.

Abstract: A system for generating and displaying a contrast false color overlay as a focus assist includes a signal divider, an automatic gain control unit, an adder, a signal reducer and a signal combiner. The signal divider receives a signal representing an image and divides the signal into a red channel signal, a green channel signal and a blue channel signal. The red, green and blue channel signals are input to the signal reducer and respectfully reduced by a percentage value. The reduced Green and Blue channel signals are input to the signal combiner and combined with the output of the adder. A luminance signal is also input or generated from the channel signals and is fed to the automatic gain control unit which produces a contrast signal whose brightness is proportional to the contrast in the image. The contrast signal is input to the adder along with a reduced version of the red channel signal where the two signals are added together, and the output of the adder is provided to the combiner.

Abstract: A system for shading graphic images for realistic rendering representative of tarnish accumulation has a display device, a central processing unit, an input device, and a memory means. The memory includes image components, shading routines, accessibility routines, display routines, and a texture map. The system modifies each image prior to display to apply shading. The system uses the accessibility routines to produce an accessibility factor for each pixel in the image. The accessibility factor is then used by the display routines to apply the desired shading to each pixel as it is rendered on the display device.

Abstract: A configurable cellular array is provided having a 2-dimensional array of cells in which each cell in the array has at least one input and output connection at least one bit wide to its neighbours. Each cell also has a programmable routing circuit to permit intercellular connections to be made. In one arrangement each cell contains a programmable function unit which includes a plurality of multiplexers. In a preferred arrangement the function unit and routing unit are programmable using associated Random Access Memory (RAM) areas within the cell. Each cell may be coupled to at least one global or array-crossing-signals so that all cells can be signalled simultaneously. The 2-dimensional array is rectangular and the intercell connections are orthogonal and are one bit wide.

Abstract: A minimal instruction set computer architecture (hyperscalar computer architecture) comprises a central memory, an instruction buffer, a control unit, an I/O control unit, a plurality of functional units, a plurality of register files, and a data router. In the hyperscalar computer architecture, the central memory transfers a plurality of instructions to the instruction buffer. The control unit receives multiple instructions from the instruction buffer, and automatically determines and issues the largest subset of instructions from those received that can be simultaneously issued to the plurality of functional units. Each functional unit receives data from and returns computational results to a corresponding register file. The data router serves to transfer data between each register file and any other register file, the central memory, the control unit, or the I/O control unit.

Abstract: A system for extracting and dynamically displaying data from a database comprises a central processing unit, an input device, a program memory, a display device, a printer, mass storage, and a network. The program memory comprises management records for retrieving and updating information in the database, and dynamic documents for presenting database information to the user. The information from one or more underlying commercial databases is structured and reorganized into management records. The management records interact with the dynamic documents to reformat the data into the form desired by the user. Both the management records and dynamic documents are also used to execute operations on the data in the database such as sorts, filters, and logical and mathematical functions. The present invention also include a plurality of unique methods for extracting and updating data in the underlying databases.

Abstract: A system for managing I/O requests directed to a disk array comprises a processing unit, predetermined amounts of Random Access Memory (RAM) and Read-Only Memory (ROM), an operating system, a virtual disk driver, an input device, an output device, and a disk array. The virtual disk driver comprises a request modification memory, a pending queue, an active queue, a stripe buffer, a span buffer, and a parity buffer. The system breaks each I/O request received into one or more subrequests according to request type, request length and the storage capacity of a sector-row within the disk array. Subrequests are entered into a pending queue in first-in, first-out (FIFO) order. Subrequests within the pending queue corresponding to write operations directed to a common sector-row are merged into a corresponding array request. Each array request is stored in an active queue. Once the number of array requests exceeds a predetermined constant, each array request is issued to the RAID type disk array.

Abstract: An apparatus for combining a foreground pixel signal and a background pixel signal according to a blending factor signal to generate a composite pixel signal comprises first, second, and third registers; a signal selecting multiplier; and at least one adder. The first, second, and third registers store the foreground pixel signal, the background pixel signal, and the blending factor signal, respectively. The signal selecting multiplier uses the signal within the third register to selectively shift and add the signals within the first and second registers, resulting in a compound pixel signal. Each adder is used to combine the compound pixel signal with a correction signal, producing an approximation signal. A subset of bits within the approximation signal correspond to the composite pixel signal.

Abstract: A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.

Abstract: A programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data. A switch on the output of the configuration memory controls the selection of the configuration data applied to the configurable logic block. Each configurable logic block has one data storage device per set of configuration data. The configurable logic blocks may be re-configured within a user's clock cycle.During a first period, the switch on the output of the configuration memory selects and passes configuration data from the first set of configuration data. The configurable routing matrix and configurable logic block are configured according to this first set of configuration data and store results in a first storage device. During a second period, the switch selects and passes the second set of configuration data.

Abstract: A cutoff wall liner joining method includes the steps of: (1) excavating a slurry trench; (2) positioning a first layer of liner material within the excavated trench; (3) positioning two pipes adjacent to the liner material in such a manner as to form a substantially S-shaped configuration of the liner material around the pipes; (4) back filling a portion of the trench adjacent a first one of the pipes; (5) removing the other, second one of the pipes; (6) excavating an additional portion of trench extending away from the back filled portion; (7) positioning a second layer of liner material within the newly excavated portion to form a overlapping portion of liner material; (8) positioning a pipe adjacent to the remaining pipe in the trench such that it overlays the overlapping portion of liner material, then positioning a third pipe in the excavated additional trench portion; (9) back filling a portion of the trench adjacent the third pipe; (10) removing the third pipe; (11) back filling the space left by the

Abstract: A soil mixing apparatus that requires less drilling force comprises a shaft, a plurality of cutting blades, an excavation blade, an auger bit, a shear blade having an extendible finger. The cutting blades, excavation blade and auger bit are attached to rotate with the shaft. The shear blade is attached at a fixed longitudinal position along the shaft. The shear blade provides a variable length by attaching different length fingers that are adjustable to the soil conditions in which the mixing apparatus is used. The shear blade is also mounted to the shaft at an angle such that the shear blade rotates in the same direction as the excavation blade and the cutting blades, but at a much slower rotation rate.

Abstract: A distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value. Each node system of the present invention comprises a CPU, an input device, a display device, a printer or hard copy device, a given amount of RAM and ROM memory, a data storage device, a local clock, a transmitter/receiver, an antenna, a virtual master clock processor, and a common data bus. The method of the present invention comprises the inclusion of a node's local clock value in a message just prior to transmission over the network, storage of a node's local clock value in RAM after an incoming message has been received, and the calculation of the time delay between the sending node and the receiving node by the virtual master clock processor.

Abstract: An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit.

Abstract: An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged.

Abstract: A special purpose modular receptacle comprises a generally rectangular housing having an opening which exposes a cavity within the housing. A plurality of electrical contacts are disposed within the cavity of the housing. Terminal ends of the contacts electrically connect to corresponding contacts on a standard modular connector or a modified modular connector inserted into the cavity. The contacts are exposed at a lower rear portion of the housing allowing connection between the contacts and a printed circuit board. Attachment means allow physical and electrical connection of the housing to a printed circuit board. A guiding means may be present as a modular connector insertion aid.

Abstract: A system for proactively automating the use of a computer comprises a central processing unit (CPU), an input device, a display device and memory including a set of feature templates, context monitoring unit, input monitoring unit, feature presentation routines and feature implementation routines. The CPU is coupled to the display device and input devices for displaying information and receiving information, respectively. The CPU is also coupled to the input monitoring unit and the context monitoring unit to detect and record user manipulations of the input device and its context. The CPU is also coupled to a section of memory containing feature templates. Each template is a set of input manipulation steps and program contexts. The CPU compares the recorded user manipulations of the input and their corresponding program context with the feature templates stored in memory.

Abstract: A special purpose modular connector comprising a generally rectangular housing having a central body portion and two extending side arm portions. A plurality of electrical contacts are disposed within the body and arm portions. Slots at a front end of each portion of the housing expose a terminal end of each electrical contact. Openings in the rear portions of the housing allow connection of cables or other types of component wiring to the contacts. A locking tab is formed at the underside of the housing and functions to align and securely connect the special purpose modular connector with a correspondingly modified receptacle.

Abstract: An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing circuit, an opcode storage register, and a pointer storage register. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC to an instruction address bus, transferring the host instruction stored at the address indicated by the VPC to the instruction bus for issue to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the state machine prefetches the nest emulation routine pointer (NERP) by issuing DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means.