Abstract: A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.
Type:
Grant
Filed:
June 29, 2000
Date of Patent:
June 10, 2003
Assignees:
Sony Corporation, Sony Electronics Inc.
Inventors:
Glen D. Stone, Scott D. Smyers, Bruce A. Fairman