Patents Represented by Law Firm Groover & Bruning
  • Patent number: 5367727
    Abstract: A waterbed structure, in which added lumbar support is provided by a padded cover atop the bag (which also provides extra thermal insulation and padding). The padded cover includes a sheet of convoluted foam which covers essentially the full length of the mattress. This sheet of convoluted foam is stiffened, over the middle part of the mattress length, by a complementary piece of convoluted foam which is mated with it. The increase in thickness caused by having two pieces of convoluted foam face-to-face is relatively small. Thus, this arrangement provides extra firmness under the torso, while maintaining an essentially flat upper surface.
    Type: Grant
    Filed: October 7, 1992
    Date of Patent: November 29, 1994
    Assignee: Valwhat Enterprises, Inc.
    Inventor: Charles D. Dyer, Jr.
  • Patent number: 5221910
    Abstract: A CMOS integrated circuit incorporating both logic functions and analog functions. The latter are subjected to noise from the logic transitions by means of supply conductors. To avoid disturbing the rest point of an amplifier by this supply noise, without using compensation circuits which would increase the number of pins of the integrated circuit, it is proposed to supply a pair of complementary transistors forming an amplifier stage by identical incoming and outgoing current generators. These generators are transistors copying a current from a current mirror circuit which includes a pair of complementary transistors connected between the two power supply lines.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: June 22, 1993
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Christian Tournier
  • Patent number: 5198707
    Abstract: To enable a determined mode of operation, out of several possible modes, to be dictated from the exterior of an integrated circuit, there is provided a specific pin and a detector that is connected to the pin and is capable of detecting a logic level 0 or 1 or a high impedance state at this pin. The detector includes several switches and a resistor. It works in two successive phases and consumes no current at rest. A register memorizes the logic level of the pin during the two phases, and a decoder determines the state of the pin from the two memorized logic levels.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: March 30, 1993
    Inventor: Jean Nicolai