Abstract: A circuit for the generation of a high ramp voltage for the supply of voltage to a capacitive load, in particular a high voltage for the programming or erasure of at least one memory cell of a non-volatile memory, comprises floating-gate transistors as storage elements. This generation circuit comprises a P type load transistor connected by its source to the output of a voltage booster delivering a high direct and constant voltage (HIV), by its drain to the load, the high ramp voltage being available at this drain, and by its control gate to a control feedback circuit to control the load current. This circuit achieves automatic control over the slope of the high ramp voltage (Vpp). Application to the generation of a high ramp voltage whose slope is smaller than a critical slope and the maximum value is high.

Abstract: A semiconductor device includes first through fourth pads and first through third external connection leads with the first external connection lead being a ground connection lead and the first and second pads being ground pads. First through fourth connection wires selectively connect the pads to the external connection leads. Additionally, a first ground line is connected to the first pad, a second ground line is connected to the second pad, a first protective diode connects the first ground line to the third pad, and a second protective diode connects the second ground line to the fourth pad. The first external connection lead is connected to the first pad via the first connection wire and to the second pad via the second connection wire, the third connection wire connects the third pad to the second external connection lead, and the fourth connection wire connects the fourth pad to the third external connection lead.

Abstract: A compensated voltage regulator of the type used in programming non-volatile memory cells of a memory cell matrix that is divided into sectors. The voltage regulator includes a comparator that is connected to a supply voltage. A first input terminal of the comparator is supplied a reference voltage, and a second input terminal is feedback connected to a program line. The control terminal of an output transistor is connected to an output terminal of the comparator, and a conduction terminal of the output transistor is connected to the memory cells by the program line. An output current is passed through a conduction terminal of the output transistor. Further, a compensation circuit is powered by the supply voltage. An input of the compensation circuit is connected to the output terminal of the comparator and to the output transistor, and an output of the compensation circuit is also connected to the output terminal of the comparator.

Abstract: A billing system and method is disclosed for a telephone system comprising at least one central office switching system, wherein a peripheral subsystem is connected to the central office switching systems via a call connection channel, the peripheral subsystem comprising means for providing at least one auxiliary call processing capability via the call connection channel. The a billing system comprises: a billing generation means running on said peripheral subsystem for generating billing data related to said auxiliary call processing capability; a collecting means for collecting said billing data; formatting said billing data to a specified formatted output and outputting said formatted output to said central office communication network.

Abstract: The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

Abstract: Disclosed is a load pump type of voltage generator circuit designed to produce several levels of voltage higher than a supply voltage of the circuit. The circuit comprises two cascades of elementary pumping cells. Each cell is controlled by at least one driving signal. To make the two cascades work together, it is planned to modify the driving signal or one of the driving signals assigned to the last cell of the first cascade in such a way that the first cascade delivers a voltage equal to the sum of the voltages delivered by the two cascades. In a particular embodiment, the two cascades comprise the same number of cells and can work in parallel. Application to the field of non-volatile memories for the production of read and write voltages.

Abstract: A mechanism is provided, for use with a portable authorization key, such as a "Personal Area Network" (PAN) device, wherein the PAN device is to be carried by a human user and to be used for authorization for the user's use of equipment, such as a computer. Further, the mechanism of the invention is for use in situations where the user is to remain in close proximity to the equipment for a moderate-to-long period of time. The mechanism provides a physical interface for direct coupling with the PAN device. The interface includes a recharge power coupling. When the user begins a session of use of the equipment, HE gets out the PAN device and places it at the physical interface. Authorization to use the equipment is provided through the direct contact. Further, the equipment provides recharge power to the PAN device. Thus, the mechanism of the invention takes advantage of the extended period of time the user remains in close proximity to the equipment, to provide convenient recharging of the PAN device.

Abstract: A system and method are provided for facilitating proof that a specific item, such as a document, has been sent via a communication medium, such as the mail service of the United States Postal Service, at a specific time. A bit map image is produced, such as by scanning a hard copy document. Preferably the bit map is compressed into a data string and hashed. The hash file is signed by a certifying authority, such as the USPS, using an existentially unforgeable signature scheme. The original document, a code representation of the string, and a code representation of the signature are sent via the communication medium. As a result, the combination of materials sent provides proof of the authenticity of the content of the document.

Abstract: A system and method are provided, for use with a computer graphical user interface (GUI) system, for giving the user help information associated with displayed symbols, such as icons representing data objects, applications, etc. For a given icon or other symbol, a plurality of different images are provided. When help is invoked, such as in response to a user moving the display cursor onto the icon, the plurality of help images are displayed. The images may represent a sequence of actions the user is to take, in order to make use of the object represented by the icon. The images are then displayed in time sequence. The images may then include reminder images of what had taken place prior to the image currently being displayed. Alternatively, the images may represent a set of alternative uses to which the user may put the object.

Abstract: A method and apparatus for communicating between two, or more, devices receiving a variable-length bit stream. The method and apparatus allocate an input buffer larger than any read size selected for the receiving unit and the reception stops when the input buffer is full.

Abstract: The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.

Abstract: An integrated circuit comprises a microprocessor (1), a memory (2) and one or more internal peripherals (3) connected, firstly, to one another and, secondly, to circuits external (4) to this integrated circuit by means of connections circuits (5). The peripherals comprise circuits called options circuits (6) enabling the operation of these peripherals to be configured. For an operating session corresponding to putting of the integrated circuit into service, the operations of these peripherals are defined as a function of information elements stored in the the first part of the memory (7). The memory also has a second part (8) designed to store instructions that can be executed by the microcontroller. This configuration of the peripherals takes place when the integrated circuit is put into service, by the linking of said peripherals to said first part of the memory. This memory is of the programmable type.

Abstract: The present invention concerns a method for protecting a write operation of a memory cell within an integrated circuit that comprises the introduction of a random period (d1) between the reception of an external write command and the application of a physical variable to the memory cell so as to thwart the determination of the applied waveform characteristics as a function of time of this physical variable. The present invention also concerns an integrated circuit that comprises a memory whose write operation is protected according to this method. An application of the present invention is in the domain of chip carrying cards, i.e. smartcard applications.

Abstract: A method and apparatus to test the running of a program of instructions encoded on one or more words, carried out by an integrated circuit, the program being contained in a memory connected to a central processing unit by means of an instruction address bus. A stack of registers is formed and this stack is connected to the instruction address bus in such a way that the address of the first word of each instruction carried out is stored in the stack at the time when it is carried out.