Abstract: A microprocessor-based turbine speed controller which incorporates a set of permanently programmable memory devices for characterizing the control of turbine speed in real time is disclosed. A speed monitoring interface circuit included in the speed controller is governed by the microprocessor in accordance with the processing of one program stored in one or more of the permanently programmable memory devices to generate speed measurement data words representative of actual turbine speed. In addition, a power-on initialization circuit initializes the microprocessor at the time of power turn-on to process another program stored in one or more of the permanently programmable memory devices for initializing a plurality of predetermined registers contained in the speed controller corresponding to the characterized speed control operation to be performed by each. Further apparatus and programmed instructions for the control thereof are employed to detect a malfunction in program execution by the microprocessor.

Abstract: An improved method for growing the silicon oxide memory insulator of an MNOS memory transistor is disclosed. The oxide is grown by passing a mixture of inert gas and anhydrous HCL over the substrate while the temperature is maintained within a predetermined range.

Abstract: A method for making a sloped insulator for use in a solid state device is also described in which the surface of the insulation layer which is oppositely disposed from the interface of the insulation layer with the semiconductor wafer is provided with areas having a controlled slope with respect to the plane of the insulation-semiconductor interface.

Abstract: A digitally controlled microwave phase lock loop for switching rapidly from one lock frequency to another is disclosed. A digital word corresponding to a desired input voltage for a selected frequency is converted to an analog voltage for application to the coarse tuning port of the loop's voltage controlled oscillator. Prior to switching to another frequency, the error voltage for the fine tuning port is compared with a zero error reference voltage. The least significant bit of the digital word for such frequency is increased or decreased by one depending on the direction difference between the compared voltages. This incrementally changed word controls the coarse tuning voltage during the next selection of the particular frequency. The system is initialized by repetitively selecting each of the possible frequencies until the digital word for each selected frequency is within one increment of the zero error reference voltage for the fine tuning port.

Abstract: A steam turbine control system comprising a primary and an auxiliary manual turbine controller, each said turbine controller including a set of valve position setpoint controllers for close-loop control of the turbine steam admission valves, is disclosed. Each valve position setpoint controller operates, at times, on a position error signal to generate a valve position control signal which controls the rate of valve position movement of a corresponding turbine steam admission valve. The steam admission valves are closed-loop controlled by a selected set of said primary and auxiliary valve position setpoint controllers. The set of valve position control signals corresponding to the selected set of position setpoint controllers are coupled to their respective turbine steam admission valves for controlling the rate of position movement therein. The valve position error and position control signals of the unselected set of said controllers are maintained at approximately zero potential.

Abstract: A vibration noise filtering system for use in airborne radar master oscillator, RMO, systems is disclosed. Master and slave crystal oscillators are used, the slave oscillator being phase locked to the master oscillator governed by a phase locked loop, PLL, having a predetermined low frequency bandwidth. The master oscillator is structurally coupled directly to a source of vibration of the aircraft, while the slave oscillator is isolated and supported from the vibration source by a mechanical passive isolator having a resonant frequency well within the low frequency bandwidth of the PLL. The output of the slave oscillator which is the source of the RMO signal has a phase spectral density within the phase stability requirements of a typical RMO across the operating modulating frequency ranges of both air-to-ground and air-to-air radar modes.

Abstract: A process and structure are disclosed whereby dopants are used to surround crystalline defects in a semiconductor crystal thereby creating a PN junction which isolates the defect site from the remaining semiconductor substrate and preventing charge flow through the defect into the potential well of a charge coupled device structure.

Abstract: A method and apparatus is described for the post processing of return signal data in a single channel medium PRF pulse doppler radar receiver. The disclosure is directed to preventing sidelobe return signals from being displayed as "ghost" or "false" targets. The received signal data is preliminarily processed by a filter bank and a CFAR threshold circuit to remove main beam clutter and area sidelobe clutter returns. The preliminarily processed data is then temporarily stored as two parallel correlations are performed on a range cell by range cell basis to identify range cells which contain discrete sidelobe clutter return signals. One of the parallel correlations is performed on the data after it has passed an STC (Sensitivity Time Control) threshold circuit and the other parallel correlation is performed on the raw data. The outputs of the parallel correlators are compared.

Abstract: A method and apparatus for the processing of return signal data in a single channel, medium pulse repetition frequency, pulse doppler radar receiver in which discrete sidelobe return signals are prevented from being recognized as true targets. The return signal data is processed by a clutter cancellation circuit, which in the preferred embodiment is a doppler filter bank, to remove main beam clutter and a constant false alarm rate threshold circuit to remove area sidelobe clutter return signals. The return signal data is temporarily stored as data blocks which are representative of the return data in the interpulse period of each pulse repetition frequency. The data blocks are unfolded over a predetermined range and two parallel correlations are simultaneously performed over the predetermined range to identify discrete sidelobe clutter return signals.

Abstract: A memory system utilizing an array of dual gate variable threshold MNOS memory transistors is disclosed which may be operated such that a single MNOS transistor is used to store each bit of digital information or in a second mode which utilizes two MNOS transistors for each bit stored. The threshold of the transistor interrogated is used to determine the state of a flip-flop comprising a pair of cross-coupled MNOS transistors. A particular transistor of the array is interrogated by coupling appropriate "row select" and "column select" signals to the row and column select terminals. Transistors comprising the first and second columns have their source terminals connected in common and to the drain terminal of the first transistor of the cross-coupled pair. Similarly for, the third and fourth columns. First and second reference transistors also have their source terminals respectively coupled to the drain terminals of the first and second transistors comprising said cross-coupled pair.

Abstract: A system for indicating optimum positioning of steam inlet valves to minimize steam throttling losses during operation of a turbine power plant in the sequential valve mode is disclosed.

Abstract: A phase lock loop system that includes a voltage controlled oscillator. The output of an integrator provides the voltage to a tuning port for determining the precise frequency and phase of the oscillator. In response to a change in frequency, the input to the integrator is switched off at the precise time that its output voltage reaches the value for the proper phase relationship at the new frequency. The output of a low pass filter fed by the loop's phase detector determines such precise time. At said precise time, the stabilized condition of the loop is sensed and corrected for minor deviations.

Abstract: An expendable signal repeater for transmitting a replica of received signals in which the received signals are converted to an intermediate frequency by mixing in a down-converter with an upper harmonic of a heterodyning signal provided by a local oscillator; the intermediate frequency signals are delayed; and the delayed, intermediate frequency signals are converted to the transmitted signal by mixing in an up-converter with the upper harmonic of the amplified, local oscillator heterodyning signal. A mechanism is provided for switching the local oscillator between the down-converter and the up-converter during the delay of the intermediate frequency signals to prevent feedback of the transmitted signal.

Abstract: A radiometer in which independent thermal signals are combined to form first and second receiver channel input signals that are coherent with respect to each other. The first and second receiver channel input signals are independently processed in parallel receiver channels to provide first and second correlation signals, each of which include a thermal signal component and a noise signal component. The first and second correlation signals are then correlated to provide an output signal for the radiometer.

Abstract: An improved corner turn memory addressing system and method for radar wherein digital data corresponding to the reflected value of each radar pulse for successive range gates is written in sequence, and such digital data for each range gate for succesive radar pulses is read out, in sequence, is disclosed. As each data item is read out of a selected address of a memory, a new received data item is written into the same address. A single data value is summed with each previous address to determine the subsequent address for each data item of a single radar "look". A repetitive series of different data values is used for successive radar "looks". When the sum of the added value and the previous address equals or exceeds the total number of data items for each "look", such sum has subtracted therefrom a data value corresponding to (N .times. M - 1) to determine the next address, where N is the number of range gates and M is the number of radar pulses for each radar "look".

Abstract: A receiver and method for detecting a Manchester coded waveform is disclosed. The waveform is clocked to provide a number of digital samples of each positive and negative pulse. Each positive pulse is validated provided that a predetermined number (k) of the total samples (N) is more positive than a positive (+T) threshold level and a predetermined consecutive number (j) of the samples (N) are more positive than a negative (-T) threshold level. Each negative pulse is validated provided that (k) of (N) samples is more negative than the -T threshold level and (j) of (N) are more negative than the +T threshold level. Each data bit pulse synchronizes each succeeding data bit pulse by providing a predetermined time interval during which the midpoint of each pulse must change between a positive and negative waveform.

Abstract: In a medium PRF pulse doppler type radar receiver, target detection is achieved in both search and track modes. In the search mode, the video signal from the receiver section is notch filtered to cancel the main beam clutter. The remainder of the signal is threshold detected, followed by ranging each of the thresholded signals to resolve the range ambiguity of the signals. The unambiguous signals are gated through a range sensitive threshold which operates along a power curve of R.sup.4, resulting in true target returns being thresholded by the range sensitive threshold circuit and blocking out discrete sidelobe returns. In the track mode, the video signal from the receiver is clutter cancelled to remove main beam clutter, as in the search mode, and the remaining signals pass through a velocity track filter with a narrow band window.

Abstract: The proposed general-purpose, fully-analog device is capable of such functions as auto-correlation, cross-correlation, convolution, transversal filters, etc. at high speeds (one megahertz typical sample rates) with no analog-to-digital or digital-to-analog conversions. The device correlates analog samples in one CCD channel against analog samples in a second CCD channel by means of balanced MOSFET's which multiply the associated voltage samples to give current products that are summed for all multipliers. The two CCD channels include unique floating-clock sensor and buffer circuits which sense the CCD charge samples without affecting the efficiency of their propagation along the CCD shift register.

Abstract: A digital system for processing return energy in a aircraft pulsed doppler radar system which includes a wave energy transmitter and a receiver for detecting the wave energy returned to the receiver by reflection. A digital signal processor develops target and noise information from the return energy and the return energy related information is supplied to a digital computer. The computer determines the range from which the return energy is reflected and provides digital range data. The width of the return energy in the time domain and the amplitude of the return energy are evaluated to provide digital width and digital amplitude data. The return energy is designated as clutter and clutter AGC and blanking signals are generated to control the receiver in response to an evaluated width and amplitude of the return energy above predetermined minimum values.

Abstract: A bucket brigade analog-to-digital converter, which is a charge coupled analog-to-digital device that is made up of successive stages with each stage in one aspect including potential wells, and in another aspect including capacitors is disclosed. The charge or portion thereof in each stage is passed on to each successive stage in response to clock pulses, and compared in each stage with a different predetermined reference charge or voltage. The comparator output of each stage constitutes one bit of digital data.