Patents Represented by Attorney H. Warren Burnam, Jr.
  • Patent number: 7327433
    Abstract: Each of a pair of substrates respectively comprises an electrode and a rubbed alignment film on one surface, while the other surface is provided with a polarizer. The substrates are placed so that the surfaces provided with the alignment films are opposed to each other, and the area between the substrates is filled with a medium to form a material layer. Then, a medium made of a negative-type liquid crystalline compound sing a photopolymerizable monomer and a polymerization initiator is injected into the material layer held between the substrates. Further, ultra violet irradiation is performed with the medium exhibiting a liquid crystal phase, so that the photopolymerized monomer is polymerized, thus forming a polymer chain. In this manner, obtained is a display element, that causes change in degree of optical anisotropy in response to application of electric (external) field, which display element can be driven by a lower intensity electric (external) field.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: February 5, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koichi Miyachi, Seiji Shibahara, Iichiro Inoue, Shoichi Ishihara, Takako Koide
  • Patent number: 6125469
    Abstract: A magnetic disk storage device employing an on-the-fly, multiple burst error correction system for detecting and correcting errors in data sectors stored on a magnetic disk, wherein each data sector comprises a data field and multiple sync marks for synchronizing to the data field. Multiple sync marks improve the probability of successful byte synchronization to the data field in the presence of noise in the system, such as defects in the storage medium. Further, a sync mark may be embedded within the data field to facilitate byte resynchronization when synchronization is lost.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: September 26, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Christopher P. Zook, Neal Glover, John J. Schadegg, Jr.
  • Patent number: 6018626
    Abstract: An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: January 25, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook
  • Patent number: 5727003
    Abstract: An error correction system (20) operates on clock cycles to decode a sequence of error correcting symbols (R(x)) received from a disk drive (24), and alternatively to encode data in a codeword for storage on a disk drive. The system includes a generator (30) which, during decoding, receives symbols of the sequence during a plurality of reception clock cycles. During the reception clock cycles the generator generates error pattern bits, regenerated CRC values, syndromes, and parity values. Also during the reception clock cycles the generator uses the regenerated CRC values and CRC symbols of the sequence to generate CRC check values. An error address determinator (90) uses the syndromes and parity values to determine, during a last of the reception clock cycles, a reference address (L) of an error burst in a data symbol portion of the sequence. An error pattern generator (80) then efficiently inserts the error pattern bits at the reference address in an output error pattern during a very next clock cycle.
    Type: Grant
    Filed: July 3, 1995
    Date of Patent: March 10, 1998
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook