Abstract: A printed wiring board comprised of a plurality of keys or switches, which form a keyboard, for entry of data or changing the function of an electrical circuit. Each key comprises a flexible conductive actuating element and at least two conductive contacts which are affixed in a nonplanar relationship to the substrate of a printed wiring board. The actuating element is caused to come in contact with the conductive contacts when the actuating element is depressed, thus closing the switch.

Abstract: An integrated semiconductor circuit has a portion thereof divided into a plurality of air isolated mesas which constitute a heater element array. A heater transistor formed within each mesa is selectively turned on in response to logic signals to heat one mesa of the array. By selectively heating the correct mesas, an area of the mesa array corresponding to a desired character is heated. Thermally sensitive material on which a dynamic display is formed or on which a permanent display is printed is in thermal contact with the material of the heater element array. Also formed within each mesa is its corresponding driver transistor.

Abstract: A multiple block binary synchronous duplex communications system provides for the orderly transfer of data from one location to another utilizing communications facilities. This communications system increases the efficiency of data links with long propagation delays or with long processing times at either end by maintaining a continuous flow of data and responses in both directions. The memory of the communications link is kept full at all times. Data is transmitted in blocks including an identification code. The received data is checked for errors. When errors occur the transmission of data is not stopped; data is continuously transmitted and signals are returned including the block identification of the block containing the error. The block containing the error is then retransmitted when the transmitting station of the communications system is available for this task.

Abstract: In a long line data acquisition system, an input network is provided for coupling the lines to a data acquisition unit. The network includes the cascade combination of a first filter presenting a low pass frequency response to common mode voltage and a second filter presenting a low pass frequency response to difference mode voltage. The output of the second filter is coupled to an amplifier having high common mode rejection. The network substantially reduces, at the amplifier input, both common mode and difference mode noise picked up by the lines.

Abstract: An inertia isolator is mounted on the frame of a web transport system between a drive roller and a supply reel on which web material is wound. A first relatively stiff member is mounted to the frame adjacent the drive roller and a second relatively stiff member is flexibly attached to the first member and positioned so that the web material is in slidable contact. The second member flexes in a direction to aid in unwinding the web when the drive roller is accelerated and flexes in the other direction when the drive roller is decelerated.

Abstract: The specification discloses a technique for suppressing the effect of noise generated during the introduction of a charge into a potential well of a charge coupled device. The technique involves detecting the voltage appearing on a floating diffused region during the introduction of the charge through the floating diffused region into the CCD potential well. An error signal is developed from the detected voltage and is subsequently utilized to extract noise from the output electrical signal of the CCD.

Abstract: Electrical signals representing analog values of variables to be measured are sampled and multiplexed onto a common conductor. When the analog values are generated by transducers having a logarithmic characteristic, the signals are linearized by a log amplifier prior to being multiplexed. The ranges of the analog signals are made similar to facilitate use of a common display. A single analog-to-digital converter generates digital outputs representing the amplitudes of the respective analog samples and the digital outputs control display logic for operating the common display. A sequence timer controls operation of the multiplexer, analog-to-digital converter, display logic, and the display itself. Facility for manual override to display selectively any of the variables is provided, as well as an alarm indicator for generating an audible or visual alarm signal in the event any variable exceeds (or drops below) a predetermined reference level.

Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology is fabricated on a relatively small semiconductor chip resulting in high yield. The segment and digit drivers which are fabricated on the same semiconductor chip utilizing I.sup.2 L techniques have grounded emitters requiring a relatively large power drain to produce blank segments. A unique feature of the calculator is an automatic blanking circuit which turns off both the segment and digit drivers for blank digits to provide no power drain while selectively enabling the digit drivers and segment drivers so that the keyboard can be scanned utilizing the same digit drivers.

Abstract: A capacitor of limited storage capacity is charged and discharged under control of a switching arrangement. The switching arrangement functions to connect the capacitor to a first steady current source of one polarity for a fixed first interval in each cycle of an input signal, and connects a second steady current source of opposite polarity to the capacitor for the remainder of the input signal cycle so that the voltage stored by the capacitor changes polarity when the frequency of the input signal traverses a threshold value. By shunting the capacitor with a fixed resistor, an output voltage linearly dependent on the input frequency can be obtained. By connecting the switching arrangement to connect the first current source to the capacitor for a fixed interval of time in each cycle of a first input signal, and to connect the second current source to the capacitor for a fixed interval of time in each cycle of a second input signal, a difference frequency discriminator function can be provided.

Abstract: A CCD shift register involves a serial input channel and a serial output channel interconnected by a plurality of parallel channels formed in a semiconductor body with separate arrays of multi electrode sets of phase electrodes overlying the input, parallel and output channels. A summing gate electrode common to all of the parallel channels is adjacent the output channel. Control means actuates the gate to transfer charge packets from each parallel channel into the output channel and clocks the charge packets to the output. Two such shift registers are provided with means to inject time samples of an input signal alternately to the two shift registers and to multiplex the outputs therefrom.

Abstract: An improved charge transfer device signal processing system is disclosed. In one aspect of the invention the signal at each node of a bucket brigade delay line is detected to provide a continuous output signal over a major portion of a cycle of a multiphase clock. In a different aspect of the invention the signals detected at the respective nodes of a matched filter are selectively summed to negative or positive summation busses to provide an electronically programmable matched filter. In still a different aspect of the invention a charge transfer device matched filter is provided in which both the magnitude and sign of the respective weighted signals can be selectively controlled. There is also provided an improved configuration for detecting the charge required to recharge the two different electrode portions of a split electrode weighted charge coupled device matched filter.

Abstract: The specification discloses a technique for non-destructively sampling the charge stored adjacent distributed phase electrodes in a charge coupled device. A storage capacitor is provided with a capacitance in the range of the combined capacitance of the phase electrodes. A first switch is operable during a first clock period for connecting the capacitor to a source of reference voltage. A second switch is operable during the first clock period for connecting the phase electrodes to be sampled to circuit ground. An insulated gate field effect transistor is connected with its source and drain between the phase electrodes and the second switch. The gate of the transistor is biased at a voltage level less than the reference voltage.

Abstract: The specification discloses a circuit for sampling charge stored adjacent a phase electrode in a charge coupled device and for selectively weighting the sampled charge. The circuit includes a first insulated gate field effect transistor connected at its source to one end of the phase electrode and connected at its drain to receive a clock. A predetermined first voltage is applied to the gate of the first transistor. A second insulated gate field effect transistor is connected to the other end of the phase electrode and is connected at its drain to receive a clock. A preselected second voltage is applied to the gate of the second transistor in order to control the percentage of charging current applied to the phase electrode through the second transistor. The preselected second voltage is equal to or less than the predetermined first voltage in order to maintain the clock voltage of the phase electrode at a predetermined set value.

Abstract: Circuitry for compensating for charge transfer inefficiency related dispersion in analog charge transfer devices (CTD's) is disclosed. In one aspect of the invention the tap weights of a filter are modified in a preselected manner to provide dispersion correction. In a different configuration, a dispersion compensating filter is connected to the input of a charge transfer delay line to provide an initial signal which is the inverse of the total dispersion of the CTD. In a further aspect of the invention regenerators are inserted into a CTD delay line to provide negative feedback to previous stages of the delay line in order to compensate for dispersion.

Abstract: Semiconductor charge devices are defined to effect a serial-to-parallel conversion of analogue signal information. In one aspect of the invention, a digital signal is extracted from an analogue noise environment by a shift register correlator comprising a bucket-brigade configuration of field-effect transistors in combination with gating field-effect transistors which are effective to weight the amplitude of the data in corresponding bits of the shift register. The gates of the gating transistors are selectively connected to diffused regions of transistors of the bucket-brigade delay line to effect parallel tapped outputs therefrom. The weighted signals from the gating transistors are summed at a common terminal to form the auto-correlated output.

Abstract: The invention relates to a computer in which control means provide for high speed context switching. In a more specific aspect, the invention involves an arithmetic unit in which a workspace pointer register and control means operable on an interrupt store the contents of the workspace pointer in an element of a workspace in memory designated by the interrupt program and store in the workspace pointer register the address of the first element of the interrupt program workspace.A first register stores the address of a first element of a set of dedicated workspace elements in main memory.A second register stores the memory address of a current instruction of a problem program.

Abstract: In an integrated satellite navigation system where satellite fixes periodically establish the position of a ship plying a course within the range of a chain of radio ranging stations, ship velocities are accurately determined in the interval between satellite fixes to chart the course between fixes by establishing difference values between successive RF signal transit times for each of a plurality of radio ranging stations. A set of functions dependent upon the difference values for transit times related to each station is stored, retaining the most recent and discarding the most aged of the set. Velocity signals representative of the motion of the ship are then periodically generated by utilization of the sets of difference functions. Preferably, the sets of difference functions are modified to give the most recent members of each set the greater weight.

Abstract: Near surface anomalies in common depth point seismic surveying are identified by divergence between two records which are obtained by (1) wherein generating a set of common depth point traces with full or partial fold coverage by combining traces containing energy reflected from common depth points and detected in all or a first fraction of the surface detector spread; and (2) generating a further set of common depth point traces with partial fold coverage by combining traces containing energy reflected from the same common depth points but detected in a second fraction of the surface detector spread. The first and second fractions will not be common. Similarly, this technique is used in verifying the accuracy of static corrections applied in seismic processing since erroneous corrections give rise to anomalies which can be identified.