Patents Represented by Attorney Harold G. McGurk IV

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  • Error detection and correction memory system
    Patent number: 5206865
    Abstract: Two or more memory arrays are coupled to two or more error detection and correction (EDAC). Each memory array has a plurality of memory devices each having a plurality of outputs. The outputs of each memory are divided among the EDACs such that no more than two outputs from a single memory device are coupled to a single EDAC.
    Type: Grant
    Filed: December 17, 1990
    Date of Patent: April 27, 1993
    Assignee: Motorola, Inc.
    Inventors: Eugene H. Gruender, Jr., Douglas R. Kraft