Abstract: A color image forming apparatus includes a primary transport system for moving a photosensitive receiving member of continuous length, which is designed to receive the exposure of an original image to be reproduced forming a latent image of the original at an exposure station. The photosensitive receiving member is transported through the exposure station at a maintained constant rate of movement while assuring the transport of the photosensitive receiving member through downstream stations, involving development of the latent image and transfer of the developed image to an image receiving medium, is accomplished without causing slack, wrinkling or jamming of the photosensitive receiving member in the apparatus or distortion of the developed image during its transfer to an image receiving medium.

Abstract: A semiconductor device comprises at least one p-type and n-type LDD transistors in a pair and a standard (non-LDD) transistor in the same substrate. Appropriate p-wells and n-wells are formed in the substrate, gate electrodes deposited, p-type and n-type first diffusions made, a silicon nitride layer is deposited and removed to leave behind sidewalls on the gates, p-type and n-type second diffusions are made in the LDD transistors, the silicon nitride sidewalls are washed away with a solvent that attacks only the silicon nitride, a third diffusion is made in the standard (non-LDD) transistor(s), a phosphosilicate glass (PSG) layer is applied, contact holes are etched, and an aluminum metalization layer is applied and etched for the interconnect.

Abstract: A single-packaged central processing unit (CPU) is formed on a substrate for a particular application in a variable word length computer system that includes a program memory. A first semiconductor chip in the CPU is of a general purpose type and includes a plurality of elements interconnected, such as an arithmetic logic unit (ALU), a program counter, and a register. A second semiconductor chip in the CPU is mounted on the first semiconductor chip with their active surfaces facing each other. The second semiconductor chip is configured for the particular application in accordance with a particular program instruction set stored in the program memory. The second semiconductor chip includes a command register for receiving fetched commands from the program memory, a command decoder for decoding the fetched commands and for generating corresponding control signals, and a timing generator for generating system clock signals.

Abstract: A magnetic field generation mechanism is confirmed by combining a plurality of magnets that generate magnetic fields in different directions. Since the magnetic field strength of the magnet for initialization magnetic field can be increased without increasing its thickness by providing a magnet for amplification that generates a magnetic field in a direction perpendicular to the magnet for initialization, a compact, thin device can be realized utilizing a magneto-optical recording device capable of direct overwrite on switched connection multilayer film. Further, by including a rotatable biased magnet, the device can also be used on prior art rewritable magneto-optical discs.

Abstract: A method for detecting the quality of a semiconductor device using a static current that flows in a state wherein internal elements are fixed, the semiconductor device has internal elements, such as MISFETs and complementary MISFETs in particular. By using a pattern group that controls the state of nodes of the internal elements or ON/OFF and other states of MISFETs that comprise the internal elements, as a test pattern group used for this inspection, faults involving long range reliability in addition to degenerate faults and those faults detected using conventional fault simulation may be detected. In the inspection method based on static current, observability of faults at output terminals need not be taken into consideration, so that the number of patterns in the test pattern group used for inspection may be less and may be easily created.

Abstract: An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

Abstract: A character generator and method which requires reduced storage memory space for a character memory by virtue of generating bit fill patterns that fill character borders. The borders are, in turn, generated from partial borders that are local to the starting, ending, and any middle coordinate points of an imaginary baseline roughly drawn along the centerlines of strokes making up the character. As especially applied to Japanese and Chinese character sets, the character generator and method further improve on memory storage savings by separating basic characters from compound characters. The compound characters are then generated in terms of reshaped and repositioned basic characters, thus eliminating the redundancies that would otherwise exist.

Abstract: A computer system eliminates overhead due to overlapping input processing for a keyboard, etc., by two operating systems, where one is a minor operating system operating as a subprocess of the other, which is a main operating system. The system uses an interrupt from a keyboard interface for input processing. A data input from the keyboard is determined as to whether or not it has been assigned to the minor operating system. If it has been assigned to the minor operating system, the key data is written directly to the key data buffer by the driver of the main operating system. The application program executable under the minor operating system can receive key data from a keyboard driver of the minor operating system.

Abstract: Thin-film SOI semiconductor devices formed in a thin film Si semiconductor substrate layer formed on an insulating layer on a semiconductor substrate have improved electrical characteristics and reliable reproducibility of those characteristics in the mass production, which are obtained by utilizing semiconductor substrate having high concentrations of active impurities, or by utilizing voltage biased, impurity diffusion regions in the surface of the semiconductor substrate aligned beneath CMOS FETs formed in the thin film Si layer. They can also be obtained by extension of the semiconductor substrate through the insulating film to the channel region of the CMOS FETs formed in a thin film Si regions. Further, reliably reproducible contact connection of electrodes to buried thin film Si layers is also achieved.

Abstract: A micropump for pumping liquid from an entry channel to an exit channel is disclosed. The micropump is formed in a semiconductor substrate sealed by two glass substrates. The micropump includes first and second chambers and flow channel means coupled between the two chambers. The micropump also includes a valve coupled between the entry channel and the first chamber. The valve includes a flexible valve membrane positioned closer to a second side of the semiconductor substrate than to its first side for causing the valve to be or not to be in contact with the second side of the semiconductor substrate for closing or opening the valve on the glass substrate. Additionally, the micropump includes a diaphragm forming part of a flexible wall of the second chamber and positioned closer to the second side of the semiconductor substrate than to its first side. The diaphragm is responsive to external pressure for causing liquid to be pumped from the entry channel to the exit channel.

Abstract: A production method for an MIS device comprises forming an insulator layer on a semiconductor substrate, depositing a gate electrode having a conductive silicon layer on part of the insulator layer, forming a low-concentration area on part of the surface of the semiconductor substrate using the gate electrode as a mask in a self-aligned manner, depositing a refractory metal layer on the surface of both the gate electrode and insulating film, using a heat treatment process to change part of refractory metal layer which is in contact with gate electrode into a silicide and part of the refractory metal layer which is in contact with the insulator layer into a nitride layer, removing the refractory metal layer leaving that part above surface of gate electrode and a sidewall part a prescribed thickness on the sides of the gate electrode, and forming the source and drain areas on the surface of semiconductor substrate using both the gate electrode and sidewall as a mask.

Abstract: A field emission device and method for manufacturing which comprises using a diffusion mask to preserve an area of a silicon substrate for use as a cathode while all around the cathode the substrate is being diffused with oxygen to form an insulating layer. And further comprising depositing a molybdenum gate electrode layer on the insulating layer and etching the molybdenum gate electrode layer such that the diffusion mask falls off and the insulating layer is dissolved around the cathode through the hole formed in the gate electrode layer by the diffusion mask being removed. The gate electrode openings are therefore automatically and independently self-aligned with their respective cathodes.

Abstract: An integrated circuit having MIS transistors pull-up and pull-down gate input resistors of a sufficient high resistance. The high resistance values are obtained in spite of using self-aligned refractory metal silicide films by redefining available channel stoppers to form the respective first terminals of the resistors and a contact region in a lightly doped substrate or well region to form the respective second terminals of the resistors.