Abstract: A circuit arrangement provides a way of protecting a differential pair of bipolar transistors by diverting the current into an n-channel MOSFET which is driven into conduction during an ESD event and allows a larger swing of input voltage than the anti-parallel diode pair. No extra processing steps are required and the MOSFET is driven on, rather than relying on parasitic bipolar npn transistor triggering into snap-back as in the grounded gate NMOS transistor that is commonly used for ESD protection in CMOS integrated circuits. An ESD protection circuit is provided for protecting a differential pair of transistors having two input terminals.

Abstract: A transmitting/receiving station is operable in a transmitting mode and a receiving mode. The transmitting/receiving station has a transmission coil circuit with a transmission coil and conductor having a given characteristic impedance, a first end, and a second end. The conductor has its second end connected to the transmission coil circuit and has its first end connected to transmitter means for generation of a request signal and to receiver for receiving an answer signal. Additional circuits are provided in order to guarantee that the first end of the conductor has a matched termination during the receiving mode.

Abstract: A data carrier receives at least two carrier signals which are modulated in respect of the same signal parameter but with different modulation intensities. The data carrier has at least two demodulation stages, each of which having a sensitivity adapted to a modulation intensity used for a modulated carrier signal. The data carrier further has priority means capable of granting priority each time to one demodulation stage in such a manner that a demodulated carrier signal reaches signal processing means only from that modulation stage.

Abstract: A differential cascode structure is configured to propagate a data state to a static latch at each active edge of a clock. A clock generator enables the communication of the data state and its inverse to the latch for a predetermined time interval. In a first embodiment, each cascode structure includes three gates in series, the gates being controlled by the clock signal, a delayed inversion of the clock signal, and the data state or its inverse. In an alternative embodiment, each cascode structure includes two gates in series, the gates being controlled by the clock signal and the delayed inversion of the clock signal. In this alternative embodiment, each of these cascode structures is driven directly by the data signal or its inverse. The static latch obviates the need to precharge nodes within the device, thereby minimizing the power consumed by the device. The latch preferably comprises cross-coupled inverters, which, being driven by the differential cascode structure, enhance the switching speed.

Abstract: The invention provides a voltage stabilized low level driver. The driver includes a switched op-amp that controls the output of the driver to match an internal reference voltage when it is switched on. When it is switched off, the op-amp turns off the output of the driver and allows the output to be pulled up by an external device. The driver also includes a slew rate control circuit for limiting the slew rate of the high-to-low transition at the output. The driver may be used for I2C applications.

Abstract: A decimator is provided that selectively varies the output sampling rate of an integer decimating device, such that the average output sampling rate corresponds to a desired output sampling rate. The output sampling rate varies such that an output sample is provided selectively after N input samples, or after N+1 input samples, to provide an output-to-input sampling ratio that is between N and N+1. This process introduces phase jitter as the sampling frequency varies between 1/N and 1/(N+1), but if the oversampling rate is high, and therefore N is high, as is typical of many applications that employ oversampling, the relative magnitude of the phase jitter is slight. A fractional accumulator is used to control whether the output occurs after N or N+1 input cycles, and is clocked by the input sampling clock, thereby minimizing the complexity of the embodiment.

Abstract: A preamplifier for a multi-head disk drive includes a circuit that tests the connectivity of each magnetic head in the disk drive by driving each head with a small current, and detecting the flow of this current. By driving and sensing the current flowing through the magnetic heads, both open-circuit faults and bridging faults can be detected. In a preferred embodiment, each head is tested sequentially. The result of each test is stored as a bit value in a register, for subsequent access. The circuit may be activated by a test device, or by a microcontroller in an assembled disk drive. To minimize costs, the circuit is integral to the circuitry that is conventionally used to read and write information via the magnetic heads. The oscillator that is conventionally used to characterize the read heads of a disk drive is used in a preferred embodiment to control the sequencing of tests through each head.

Abstract: A transmitter has a phase modulator and a phase locked loop that has a relatively high powered voltage controlled oscillator. The phase locked loop has a phase sensitive detector for comparing a phase comparison frequency derived from the voltage controlled oscillator output with a phase modulated intermediate frequency carrier derived from the phase modulator. The phase modulator has a reference frequency source, means for deriving four quadrature phase components of the reference frequency produced by the source and phase selection means controlled by complex modulation means for deriving the phase modulated intermediate frequency carrier by random interpolation between the four quadrature components.

Abstract: The precharge of a domino logic stage is controlled based on the precharge delay of a prior domino logic stage. The precharge of the logic stage does not occur until the output of the prior logic stage corresponds to the precharge logic state. Because the precharge logic state output of a preceding stage is an inactive state of a subsequent logic stage, the logic function of the subsequent logic stage is in a non-conducting state when the output of the prior logic stage is in the precharge logic state. By providing the precharge to a subsequent stage-only after the output of the prior stage is in the precharge state, there can be no DC current flow during the precharge of the subsequent stage, and the need for an evaluation transistor to block the DC current flow during precharge is eliminated.

Abstract: In a power consumption method for a mobile radio station in a digital mobile radio system, measurements are squeezed in earlier frames of a paging block thereby avoiding that measurements of neighbor cell BCCH carriers are performed in the last frame of the paging block, thus allowing the mobile radio station to adopt a power down mode at an earlier instant.

Abstract: A voltage level shifter circuit with gate oxide protection that can provide level shifted voltages for both read and write operations for applications in memory circuits, without increasing the circuit complexity. The level shifter circuit includes a voltage level shifter and an output stage which drives a load. The level shifter circuit can be used to drive voltages greater than the gate oxide voltage limit (i.e., level shift up for memory write operations), to drive level less than or equal to a digital supply level (i.e., level shift down or no level shift for standard memory read operations), and to drive voltages greater than digital supply level but less than the gate oxide voltage limit (i.e., fast level shift up for “booted read” operations in a memory when the digital supply voltage is too low for standard read access).

Abstract: A system enabling participants in a virtual environment to select a partner for an interaction session, the system comprising attention and priority components. The attention component employs attention sense and focus spaces. The sense space comprises a sense cone, the sense cone being both contained by a sense sphere and having a sense vector along its axis. The focus space comprises a focus cone, the focus cone being both contained by a focus sphere and having a focus vector along its axis. The attention component is associated with one or more senses, each such sense having associated therewith respective sense and focus spaces. The attention component is configured to support either/both intentional interaction (interaction driven by defined explicit controls) and spontaneous interaction (interaction driven by non-intentional encounters, e.g., spontaneous “eye” contact between avatars).

Abstract: A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of both an integer divisor as well as a fraction component. The average frequency of the output signal from the fractional divider is dependent upon both the integer divisor and the fraction component, thereby providing for a finer resolution to the average frequency of the output signal. This combination of integer and fractional frequency division is particularly well suited for the generation of signals for systems that are substantially jitter-insensitive.

Abstract: The present invention provides an LDO that is stable for all capacitive loads. Because the LDO is stable for all capacitive loads, the ESR (equivalent series resistance) inherent in any capacitive load can no longer affect the equivalent value of the combination of the ESR and the capacitive load. Thus, the invention also effectively removes the ESR restrictions on the loads. According to the present invention, a low dropout voltage regulator is provided. The regulator comprises a switching element (e.g., a transistor) having first terminal for receiving an input signal, a second terminal for providing an output signal and a control terminal; a control circuit, operably coupled to the switching element, that is configured to control the switching element; and a compensation circuit having a first segment connected between the first and control terminals of the switching element and a second segment connected between the control and second terminals of the switching element.

Abstract: A repeater employs multiple threshold detectors to distinguish between signals from external devices and signals generated within the repeater. Signals that are sent from the repeater are configured to be between two threshold levels, so that a detector at one threshold level will detect an active signal, but the detector at the other threshold level will not detect an active signal. When an external signal is received on one side (A) of the repeater, it is propagated to the other side (B) of the repeater, and at the same time, the other side (B) of the repeater is configured to only propagate external signals back to the first side (A). In this manner, the internally generated signal from one side (A) is not propagated back to the same side (A), and a latch-up is avoided. In like manner, when an external signal is received at the other side (B), the first side (A) of the repeater is configured to propagate only externally generated signals.

Abstract: A system enabling priority-based operation of a virtual environment, the system having a priority component that provides priorities for avatars and non-avatar objects, such that highest priority avatars/objects have (a) enhanced rendering and (b) increased quality of service from networks and operating systems. The priority component is responsive to selected parameters, including, for example, one or more of (i) objects' relative positions, (ii) the direction, orientation and span of sense and focus spaces, (iii) participants' profiles, (iv) predetermined parameters as set by developers and/or participants, (v) social parameters, (vi) economic models and (vii) combinations of these and other selected parameters. In some embodiments, the system employs only the attention component.

Abstract: Users control the movement of avatars through a virtual space. The system keeps track of the location of the avatars and forms a picture of the virtual space for each user. Users can select themselves to act as a cameraman. The picture of the virtual space around the location of the avatar is then transmitted separately to passive viewers via a broadcast channel. Conversation between the cameraman and other users is broadcast also via the broadcast channel. The picture broadcast has a visual detail which is finer than that of the pictures received by the various users individually; movements are reproduced therein in interpolated form and are adapted in such a manner that the avatars in the broadcast signal arrive at landmarks, in time.

Abstract: A system, apparatus and method enabling a participant to control the multi-dimensional kinetics of their avatar in a virtual environment. The participant accomplishes this control by selectably transitioning among various movements (“motion states”) from which are derived avatar motions and motion-related positions. The participant's motion states not only comprise interaction data and are correlated to avatar motion, but also are associated with selected, minimal actual motion in the participant's physical surroundings. The apparatus comprises a mount, a motion base and a support: the mount interfaces with the participant, enabling the participant to have a selected range of motion; the motion base is disposed relative to the mount so as to enable contact with the participant and, associated with such contact, provides for detection of the motion states; and the support couples the mount and the motion base so as to provide the relative disposition thereof.