Patents Represented by Attorney Harry John Staas
  • Patent number: 4368098
    Abstract: An epitaxial composite comprising a thin film of single crystal Group III-V wide band-gap compound semiconductor or semiconductor alloy on single crystal, electrically insulating oxide substrates such as sapphire, spinel, BeO, ThO.sub.2, or the like, and on III-V semiconductors or alloys. The thin film may be produced in situ on a heated substrate by reaction of an organic compound containing the Group III constituent, typically the alkyl metal organic, such as trimethylgallium and/or triethylgallium with a Group V hydride such as arsine, phosphine and/or stibine.
    Type: Grant
    Filed: April 7, 1978
    Date of Patent: January 11, 1983
    Assignee: Rockwell International Corporation
    Inventor: Harold M. Manasevit
  • Patent number: 4277881
    Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.
    Type: Grant
    Filed: May 26, 1978
    Date of Patent: July 14, 1981
    Assignee: Rockwell International Corporation
    Inventor: Gordon C. Godejahn, Jr.
  • Patent number: 4231051
    Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for diffused conducting lines in the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having oxidation and etch characteristics permits selective oxidation of desired portions only of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. There results semiconductor devices of minimum geometry with selective interconnection capabilities, affording VLSI circuits having increased density with improved yield and reliability.
    Type: Grant
    Filed: June 6, 1978
    Date of Patent: October 28, 1980
    Assignee: Rockwell International Corporation
    Inventors: Frank Z. Custode, Matthias L. Tam
  • Patent number: 4229754
    Abstract: A CCD imager for extracting the spectral information from impinging photons and having a multiple photon collection structure through which protons must serially traverse. The carriers generated by the impinging photons are collected by two or more collection regions in each resolution element and the ratio of the relative responses of each of the collection regions can be used to derive spectral information. The CCD imager is fabricated such that both the holes and the electrons generated by the impinging photons are collected, detected, stored, and transferred. Furthermore, the collection of both the holes and the electrons generated by the impinging photons in the CCD imager enables the generation of spectral information without degradation of detector quantum efficiency and can further enable the generation of complete spectral information when used to detect impinging photons comprising mono-energetic optical signals.
    Type: Grant
    Filed: December 26, 1978
    Date of Patent: October 21, 1980
    Assignee: Rockwell International Corporation
    Inventor: Barry T. French
  • Patent number: 4229755
    Abstract: A method of fabricating very large scale integrated circuits including N-channel silicon gate nonvolatile memory elements and additional peripheral transistor elements. The nonvolatile memory elements are fabricated as PDS protected drain-source devices composed of a variable threshold memory device having a thin silicon dioxide gate insulator in combination with a pair of fixed threshold devices having a thicker silicon dioxide gate insulator arranged with a common silicon nitride layer and common gate electrode. The additional fixed threshold peripheral transistors are fabricated without a silicon nitride layer. In addition, the method contains no processing steps subsequent to the fabrication of the PDS devices which necessitate the application of temperatures in excess of 900.degree. C.
    Type: Grant
    Filed: August 15, 1978
    Date of Patent: October 21, 1980
    Assignee: Rockwell International Corporation
    Inventor: Frank Z. Custode
  • Patent number: 4221044
    Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliabilty. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.
    Type: Grant
    Filed: June 6, 1978
    Date of Patent: September 9, 1980
    Assignee: Rockwell International Corporation
    Inventors: Gordon C. Godejahn, Jr., Gary L. Heimbigner
  • Patent number: D246479
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: November 22, 1977
    Inventor: Kiyoji Asano
  • Patent number: D252222
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252223
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252224
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252225
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252226
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252227
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252228
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252229
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252230
    Type: Grant
    Filed: December 4, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252231
    Type: Grant
    Filed: December 4, 1975
    Date of Patent: June 26, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252290
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: July 3, 1979
    Inventor: Kiyoji Asano
  • Patent number: D252291
    Type: Grant
    Filed: December 4, 1975
    Date of Patent: July 3, 1979
    Inventor: Kiyoji Asano
  • Patent number: D255697
    Type: Grant
    Filed: December 2, 1975
    Date of Patent: July 1, 1980
    Inventor: Kiyoji Asano