Abstract: A circuit and method for providing VGA display data to a display of lower resolution, such as an LCD panel, is disclosed. The circuit detects a write to the Frame Buffer that stores the full resolution VGA image, determines the address within the Frame Buffer that was changed, then translates the Start Address of the circuit such that the recently updated data will be displayed at or near the center row of the display. The circuit blocks accesses to display data outside the range of data displayed on the lower resolution display such that the operation of the circuit is transparent to a conventional VGA controller, thereby providing automatic virtual display panning for VGA data that is displayed on a lower resolution display such as an LCD panel.
Abstract: The present invention relates to a switchmode power supply (SMPS) high voltage start-up integrated circuit (IC) with output voltage sensing and output current limiting. The high voltage start-up IC allows low voltage pulse width modulated (PWM) controller ICs to operate directly off rectified AC lines of up to 450 VDC. The high voltage start-up IC allows PWM controller ICs to start-up with a start threshold larger than its operating voltage. The output voltage is monitored internally so that the internal high voltage switch turns off when the output voltage decreases below an internally set trip point voltage (V.sub.off) The internal high voltage switch remains off and an external auxiliary voltage is generated and applied to the output voltage. If the output voltage falls below a lower set trip point voltage (V.sub.reset) the internal high voltage switch turns back on. This allows the start-up circuit to reset itself when the PWM controller IC's auxiliary voltage does not power up properly.
Abstract: A voltage regulator which will clamp the row voltage of a memory cell or array. The voltage regulator will clamp to a value which is greater than the erased threshold voltage of the memory cell and less than the worst case programmed threshold voltage of the memory cell. The voltage regulator uses an unprogrammed memory cell of the memory array for allowing the row voltage outputted by the voltage regulator to be self-tracking over manufacturing process variations and ambient environmental influences. A switching circuit is coupled to the unprogrammed memory cell for clamping the row voltage outputted by said voltage regulator below the programmed threshold voltage level.
Abstract: The present invention relates to a high voltage output circuit for driving a gray scale flat panel display. The high voltage output circuit eliminates the inaccuracies of prior art output circuits by using a plurality of transistors to eliminate a dead band level within the output circuit. The output circuit is also less expensive than prior art output circuits since a level translator is not required.
Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.
Type:
Grant
Filed:
March 8, 1996
Date of Patent:
September 22, 1998
Assignee:
VLSI Technology, Inc.
Inventors:
Gregg D. Lahti, Gary D. Hicok, Scott E. Harrow
Abstract: The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.
Type:
Grant
Filed:
April 8, 1996
Date of Patent:
September 15, 1998
Assignee:
VLSI Technology, Inc.
Inventors:
Franklyn H. Story, David R. Evoy, Peter Chambers, Lonnie Goff
Abstract: A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.
Abstract: A system and method is shown for exercising a user's motor skills and concentration, comprising, in combination, a controller for providing a plurality of visual images and sounds, a first sensor for providing an input to the controller when activated by a hand on a selected right or left side of the user, a second sensor for providing an input to the controller when activated by a foot on the selected side of the user, a third sensor for providing an input to the controller when activated by a hand located opposite the selected side, and a fourth sensor for providing an input to the controller when activated by a foot located opposite the selected side. The system displays a plurality of visual images where each visual image contains four separate quadrants corresponding to the first, second, third, and fourth sensors.
Type:
Grant
Filed:
July 2, 1996
Date of Patent:
September 8, 1998
Assignee:
1-O-X Corporation
Inventors:
Edward J. Kozak, James L. Bailey, John W. Quinley
Abstract: The present invention is an all solid state chassis for controlling a bowling pin pinspotter. The solid state chassis is designed to replace current electromechanical chassis such as the AMF 8270 chassis, while providing new and unique capability in diagnostics and communication. The solid state chassis is designed to reduce the energy consumption of the pinspotter. The solid state chassis is also designed to detect and provide self protection against faults and overloads. The solid state chassis also allows for remote communication with the pinspotter via a hardwired communication link or by electromagnetic means.
Abstract: The present invention is directed to an improved frozen drink and dessert dispenser and method therefor. The improved frozen drink and dessert dispenser and method permits the simultaneous or alternate dispensing of two products. Further, through a dispensing valve system controlled by a controller, residue of dispensed product is purged from the product dispenser prior to the dispensing of the next serving of product and product may be dispensed in predetermined amounts. The improved frozen drink and desert dispenser and method also permits the automated cleaning of substantially all of the dispenser without any significant disassembly of the dispenser.
Abstract: A progressive start-up charge pump that eliminates the start-up problems of p-channel charge pump stages by starting the charge pump one stage at a time. The charge pump has a plurality of charge pump stages wherein each of the plurality of charge pump stages are coupled to a successive charge pump stage in a cascade mode. An enabling circuit is coupled to each of the plurality of charge pump stages for individually starting each of the plurality of charge pump stages one charge pump stage at a time starting with a last charge pump stage and successively turning on a directly previous charge pump stages until the first charge pump stage is started. This will ensure that the voltage output node is at a greater potential than the voltage input node for each of the plurality of charge pump stages during start-up.
Abstract: The present invention relates to a system and method for starting and maintaining a Central Processing Unit (CPU) clock even though the CPU clock is operating under a Clock Division Emulation (CDE) scheme. Break Events are broken into different groups with each group of Break Events being mapped to a particular programmable event timer. Each of the programmable event timers have an associated time limit which will keep the CPU clock running for a time commensurate with that group of Break Events. When a Break Event occurs, the programmable event timer associated with that particular Break Event will load the corresponding time limit into the programmable event timer. Once loaded, the programmable event timer will keep the CPU clock running during the entire time limit. Only after all of the programmable event timers have counted down will the CPU clock be allowed to stop.
Abstract: A microcontroller circuit having firmware selectable oscillator trimming includes, in combination, a microcontroller, an oscillator located within the microcontroller for providing a system clock signal for the microcontroller, and a memory portion for providing trimming data to the oscillator for trimming frequency of the system clock. The microcontroller circuit includes microcontroller logic which has the trimming data stored therein for transfer to the memory portion. Additionally, the microcontroller logic permits the user to alter the trimming data after it has been transferred to the memory portion, thereby permitting the user to alter the amount of modification of the system clock frequency from the amount associated with the trimming data.
Abstract: A patch mechanism for dynamic modification of the behavior of a state machine without interfering with normal operation of the state machine when modification is not required. The patch mechanism uses a programmable logic array for storing a modified transition and a modified output transition for an individual state of the state machine which is to be modified. A pair of multiplexer having inputs coupled to the state machine and inputs coupled to the programmable logic array are used for allowing the state machine to select either the current transition and the current output transition both defined by the state machine, or a modified transition and a modified output transition if a modification of the present state is required. A logic circuit coupled to the state machine and to both multiplexers will signal both multiplexers when it is valid to modify the present state to the modified transition and the modified output transition.
Abstract: A memory device having selectable redundancy for maintaining high endurance and high reliability. The memory device has two memory arrays wherein both memory arrays have a plurality of address locations for storing data. A switching unit is used to removeably connect the address locations of the first memory array means to corresponding address locations of second memory array in order to produce a first memory array having redundant address locations. If high reliability and redundancy is not required, a signal may be sent to the switching unit to disconnect the address locations of the first memory array from the corresponding address locations of the second memory array means to produce a memory device having an increased amount of address locations for storing data as compared to the first memory array having redundant address locations.
Abstract: The present invention is directed to a removable spacing device and method therefor, for use in the application of stucco to a building's exterior. The removable spacing device is comprised of a section of tape and a substantially triangle-shaped spacer, and is applied to the edge of a window frame, door frame, or similar structure prior to the application of a layer of stucco adjacent thereto. After the stucco layer has dried, the removable spacing device is removed, and the resulting space created by the device is filled with caulk or a similar weatherproofing material. This device and method prevents the formation of small cracks between a stucco layer and adjacent frame, which cracks are too small to be filled with caulk and which allow the damaging penetration of water into the stucco and underlying layers.
Abstract: A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information.
Type:
Grant
Filed:
June 11, 1993
Date of Patent:
August 11, 1998
Assignee:
VLSI Technology, Inc.
Inventors:
James J. Jirgal, David R. Evoy, Walter H. Potts