Abstract: A system for reading a memory cell of a memory array at voltage levels lower than an erased threshold voltage of the memory array. The system uses a voltage regulator which is coupled to the memory array for charging a desired row of the memory array to a supply voltage. The voltage regulator is further used for clamping the desired row at a voltage level which is no higher than a maximum programmed threshold voltage of the memory array. The voltage regulator is able to perform these functions while consuming no DC current. A voltage booster is coupled to the voltage regulator and to the memory array. The voltage booster is used for raising the voltage level of the desired row to a voltage above the maximum erased threshold voltage of the memory cell. This allows the memory cell to be read at voltage levels which are lower than the threshold voltage of the memory array.