Abstract: A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.

Abstract: A MOS switching circuit (1) for providing constant signal-independent gate-to-source voltage at a switching transistor (2) of a differential switched capacitor circuit so that a signal-independent resistance is provided between its source and drain includes a first control transistor (5) coupled between the input (3) and the gate of the switching transistor (2). The gate of switching transistor (2) is also coupled to a first clock phase signal PHI1 and the gate of the first control transistor (5) is coupled to a second, non-overlapping clock phase signal PHI2. A second control transistor (6) is coupled between the input (3) and the second clock phase signal PHI2 and its gate is coupled to the first clock phase signal PHI1. Capacitors (7) and (8) are coupled between the transistors (2, 5 and 6) and the clock phase signals PHI1 and PHI2, respectively.

Abstract: A method for forming a semiconductor fuse device (23) having a fuse element (20) for an igniter device, comprises the steps of providing a semiconductor substrate (12), forming an insulator layer (14) on the semiconductor substrate, forming a single active layer (16) on the insulator layer, having a predetermined depth (18) of greater than 4 microns and patterning and etching the active layer to form the fuse element (20). Preferably, the forming a single active layer step includes the step of atomic bonding an active layer to the insulator layer.

Abstract: A steering wheel shaft (103) position sensor includes a light emitter (110) fixed with respect to the shaft (103) and a pair of light detectors (111, 112) fixed with respect to the emitter (110). A disc (113) is mounted for rotation on the shaft (103) between the emitter (110) and the detectors (111, 112) and has a grey scale track extending circumferentially on the disc (113) between the emitter and one of the detectors (111), the grey scale varying from opaque to transparent to the light emitted by the emitter (110). A second, transparent track extends circumferentially on the disc (113) between the emitter and the other detector (112). The outputs of the two detectors (111, 112) are compared to provide an indication of the movement of the shaft (103).

Abstract: An object of the present invention is to contribute to increase of storage capacity of a memory and to cope with an nonlinear parasitic resistance.The non-volatile memory have a cell applying to multi-bit data by means of a double layered floating gate architecture. The cell comprises: heavily doped layers (drains 3.sub.0 -3.sub.2 and source 2) being formed separated from each other along an arrangement direction L in a semiconductor substrate; a first floating gate 4A being disposed along a direction orthogonal to the direction L between the drains and source above the semiconductor substrate; second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate above the first floating gate and lie along the direction L, close to the drain; program gates 6.sub.1, 6.sub.2 disposed correspondingly to one of the second floating gates; and a control gate 5 extending across the gate 4A above the gate 4A and being disposed along the direction L, close to the source.

Abstract: A semiconductor memory device that permits the threshold voltage Vth of a cell transistor to be measured easily and inexpensively is provided. A semiconductor memory device 1 is provided, which has a plurality of cell transistors C for storing predetermined data and is operative at a preset operating voltage Vdd, wherein during normal operation, said operating voltage Vdd is applied between a control gate and a source of each of said cell transistor C, and wherein during testing operation, a test voltage Vcc which is at lower potential than the operating voltage Vdd is applied between the control gate and source of each of said cell transistors C independently of the operating voltage Vdd.

Abstract: An object of the present invention is to contribute to increase of storage capacity of a memory. A non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture. The memory has a storage cell transistor which comprises source 2 and drain 3 being formed in a semiconductor substrate 1 distantly from each other. The storage cell transistor, furthermore comprises a single first floating gate 4A being laid between the source and drain above the semiconductor substrate, and a plurality of second floating gates 4B.sub.1 -4B.sub.n which are distant from each other and face the first floating gate. Since the second floating gates respectively store carrier corresponding to data bits and the first floating gate determines a threshold value of drain current in accordance with sum amount of carrier stored in all of the second floating gates, two or more bits data can be saved per one storage cell.

Abstract: Oscillation of the output (16, 17) of an integrated circuit output buffer (43) is automatically damped by sensing ground lead (18) transients as the buffer output (16, 17) changes, and when the ground lead (18) swing is large enough, using the sensed change to apply a turn-off signal of the appropriate polarity to a transistor (N1) serially placed in the output buffer (43) to add resistance during the transition. The added resistance damps out the oscillations quickly to prevent rebound of the buffer output voltage past the logic transition threshold (Vol). An RC time constant (R1, C1) controls the duration of the added resistance which disappears after the transition is complete. The action of a damping control circuit (45) is speed dependent so that greater damping is provided for fast transitions when oscillations would be more sever and no damping during slow transitions when damping is not needed.

Abstract: A current sourcing output stage for a high voltage operational amplifier receives a low voltage input signal (V.sub.IN) and provides a high current output signal corresponding to the low voltage input signal at an output terminal (8). A first PNP transistor (Q1) is coupled between a voltage supply (V.sub.CC) and a plurality of cascaded PNP transistors (Q2, Q3, Q8-Q11) coupled to the output terminal (8). The base of the first PNP transistor (Q1) is coupled to receive the input signal (V.sub.IN) and the bases of the cascaded PNP transistors are coupled to receive different bias voltages A control circuit (Q5-Q7, R1-R5) is coupled to the voltage supply (V.sub.

Abstract: A thin film silicon on insulator circuit with a low voltage triggered, surface silicon controlled rectifier (30) for electrostatic damage protection and method is provided. A surface silicon controller rectifier (30) is formed in a thin device layer (130), overlying a buried insulation layer (110) and electrically coupled to a low voltage trigger apparatus (36). In one embodiment, a zener diode is employed as the low voltage trigger apparatus (36), and in another embodiment low voltage trigger apparatus (36) is an n-channel MOSFET.

Abstract: An output driver that allows for static protection during generation of static discharge. The output driver includes a static protection circuit located between a predrive stage and a power drive stage.

Abstract: A telecommunications device (10) includes an input terminal (12,13) for coupling to an input line of a telecommunications network. A detection arrangement (17, 18, 23) is coupled to the input terminal (12,13) for providing an output voltage in response to a voltage on the input line exceeding a threshold level. An output terminal (21) is coupled to receive the output voltage from the detection arrangement (17, 18). The detection arrangement (17, 18) includes a control arrangement (17) for setting the threshold level in response to a received control signal (19).

Abstract: A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).

Abstract: A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof.

Abstract: An amplifier controller (104) is described for operating from a single voltage power supply (105). A switch (103) is coupled between the amplifier (102) and the power supply (105). The controller (104) includes a power conditioning circuit (106) for generating doubled and tripled voltages and positive and negative voltages for operating the controller (104) and the amplifier (102). Internal voltage regulators (138, 142) control the magnitude of the generated voltages. The controller (104) further includes: (i) a circuit (172) for disabling the controller (104) and amplifier (102) in response to an idle signal presented thereto, (ii) a circuit (178) for energizing the switch in response to a turn-on signal (128) so that the amplifier (102) can amplify, and (iii) a circuit (176) for sensing the presence or absence of negative polarity (Vss) on a second lead (188) of the amplifier (102) and, if not present, disabling the switch (103) despite the presence of the turn-on signal.

Abstract: A voltage source device for low-voltage operation which sources a desired voltage while minimizing variations in output voltage due to changes in temperature. The voltage source device includes a current source circuit having a temperature characteristic of (1/T)-a and a compensation circuit having a temperature characteristic that includes a term of -1/T, which compensates for the temperature characteristic of the current source circuit. The voltage source device also includes a voltage conversion circuit for converting the power supply current provided by the current source circuit into a power supply voltage and outputting it externally.

Abstract: A bidirectional communication system for communicating signals between a master device (1) and a slave device (2) connected by a single wire (3), in which the master device (1) includes a voltage signal generator (4) for generating voltage signals to be transmitted to the slave device (2) over the wire (3), a current sensor (6) for sensing current consumed on the wire (3), and a received signal generator (14, 19) for generating received signals corresponding to the sensed current consumption. The slave device (2) includes a receiver (7) for receiving the voltage signals transmitted over the wire and producing received data therefrom, and a current consuming device (8) for consuming current from the wire (3) in correspondence with a signal to be transmitted to the master device (1).

Abstract: An object of the present invention is to contribute to increase of storage capacity of a memory. A nonvolatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture. The memory has a storage cell transistor which comprises a semiconductor substrate 1, source 2, drain 3 and control gate 5. The storage cell transistor, furthermore comprises a plurality of floating gates 4B.sub.1 -4B.sub.n which are arranged in order between a channel and the control gate. Two or more bits data can be saved per one storage cell. According to this architecture, an integration factor per one storage cell leaps upward since a necessary number of floating gates are stacked to overlie each other, the particular number corresponding to the number of bits to be stored therein.

Abstract: A transition control circuit (2) for controlling the transitions of an output signal, at an output node (8) of a driver circuit, in dependence on the logic state of an input signal at an input node (10). The output signal being switchable between a first logic state and a second logic state. The transition control circuit (2) comprises first means (16) and second means (14). The first means (16) is enabled when the output signal has the first logic state and the input signal has the second logic state, and is disabled when the output signal has the second logic state or the input signal has the first logic state. Once enabled, the first means (16) couples the output node (8) to a first supply line (GNDA) whereby the output signal switches to the second logic state. The second means (14) is enabled when the output signal has the second logic state and the input signal has the second logic state, and is disabled when the output signal has the first logic state or the input signal has the first logic state.

Abstract: A telephone line interface circuit has a transmit path for coupling to a telephone line and a receive path for coupling to the telephone line (2). The transmit path includes a first amplifier (A1) having an output for coupling to the line (2), a first input for receiving a signal to be transmitted and a second input for receiving a first sum signal made up of a.c. and d.c. line voltage signals plus a.c and d.c. line current signals. The feedback loop thus described has sufficient loop gain to constrain the first sum signal to be substantially equal to the signal at the first input. The receive path includes a second amplifier (A4) having a first input for receiving the first sum signal, a second input for receiving substantially twice a second sum signal made up of the a.c. and d.c. line current signals plus the d.c. line voltage signal/and an output for providing receive signals.