Abstract: Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.

Abstract: A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.

Abstract: A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal.

Abstract: A touch screen includes a plurality of single-layer ITO bars having a substantially rectangular shape and arranged in parallel to each other in order to detect touches on the touch screen. The location of a touch on the touch screen in the direction along an ITO bar is determined by applying a signal on one end of the ITO bar and measuring the change in the amplitude and the delay of the signal on the opposite end of the ITO bar. Such application and measurement of the signal can be repeated with the application of the signal occurring on the opposite end of the ITO bar and the measurement of the signal occurring on said one end of the ITO bar, in order to enhance the accuracy of the measurement.

Abstract: A serial display interface such as the VESA-Display Port interface is expanded to support daisy chained coupling of one display monitor to the next. Each daisy chain wise connectable display monitor has a local daisy chain transceiver device associated with it where the local transceiver device selectively picks off passing through video data streams in response to embedded MDID identification signals and forwards the selectively picked off data to the local monitor. The local transceiver device also relays the passing through video data streams on to more downstream devices of the daisy chain. In one embodiment, the daisy chain wise connectable display monitors are hot-pluggable and unpluggable.

Abstract: A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Abstract: A method of high-speed processing and monitoring of a product, such as a pharmaceutical powder or tablet, comprises: moving the product (C) past an inspection station; illuminating at least a portion of the product with light; spectrally filtering a first portion of light carrying information about the product, o.g., transmitted or reflected light, by passing said first portion through at least one multivariate optical element (148) and detecting said filtered light with a first detector (152), —detecting a deflected second portion of said light with a second detector (156); and determining at least one selected property of the product based on the detector outputs.

Abstract: A system and method for efficient computation in the course of locating a position on the face of a touch-screen-equipped display device by limiting the amount of computations to weighted vectors within a range substantially less than the entire range of data input from the touch screen sensors.

Abstract: A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit.

Abstract: A divider can include a phase selection circuit that switches between a plurality of phase-separated clock signals in response to a fractional control signal to form a selected clock signal, the selected clock signal being utilized to generate a second clock signal; and a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the transition control signal indicating when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal.

Abstract: A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled. In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.

Abstract: A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell.

Abstract: A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.

Abstract: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value.

Abstract: A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.

Abstract: The invention relates to novel polymers or oligomers containing at least sulfinate groups (P—(SO2)nX, X=1-(n=1), 2-(n=2) or 3-(n=3) valent metal cation or H+ or ammonium ion NR4+ where R=alkyl, aryl, H), which are obtained by completely or partially reducing polymers or oligomers containing at least SO2Y-groups (Y?F, Cl, Br, I, OR, NR2 (R=alkyl and/or aryl and/or H), N-imidazolyl, N-pyrazolyl) by means of suitable reducing agents in a suspension or in a solution form. Polymer and polymer(blend)membranes which are obtained by further reacting the received sulfinated polymers, especially by alkylation of the sulfinate groups with mono- di- or oligo functional electrophiles. The invention further relates to methods for producing the sulfinated polymers and for further reacting the sulfinated polymers with electrophiles by S-alkylation.

Abstract: A method and apparatus involve: configuring a wall portion to have an opening therethrough and to have a first annular surface extending around the opening; supporting on a circuit board an electrical connector having a plurality of electrical contacts and having a second annular surface; and resisting fluid flow from one side of the wall portion to an opposite side thereof through the opening, including compressing between the first and second annular surfaces a seal ring having third and fourth annular surfaces that respectively engage the first and second annular surfaces, the electrical contacts each having a portion that is accessible through the opening.

Abstract: A boost regulator system for regulating one or more output voltages includes, a first pump element coupled to receive a first input voltage, a first switching device coupled to the first pump element, the first switching device causing a finite amount of energy to be stored in the first pump element in response to a first control signal. The system further includes, a first capacitor coupled to the first pump element and the first switching device, the first capacitor storing the finite amount of energy and generating a first output voltage in response to the finite amount of energy. A boost controller (BC) coupled to receive the first output voltage, the boost controller further configured to regulate the first output voltage by generating the first control signal.

Abstract: A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value.

Abstract: A synthetic-rubber-based composition that consists of a low-molecular-weight rubber selected from polybutadiene comprising about 75% to about 92% cis-1,4 units, sulfur, a vulcanization accelerator, and an active filler wherein the sulfur, accelerator, and active filler are each present in the form of powder having a particular particle-size range. Additionally, this composition may be used to form coatings and rubber concretes.