Patents Represented by Attorney, Agent or Law Firm Hayes, Soloway, Hennesey, Grossman & Hage, P.C.
  • Semiconductor device interconnection structure
    Patent number: 6316836
    Abstract: A semiconductor device in which an aperture of a via hole is partially overlapped with a first layer conductor, its aperture width is larger than a first layer conductor width, and the via plug is entirely covered with a second layer conductor. According to this semiconductor device, an increase of and a scattering of contact resistance between the conductors can be reduced by making the aperture area of the via hole larger.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Satoru Mayuzumi
  • Method for forming thin metal films
    Patent number: 6174563
    Abstract: A method for forming metal thin films for wiring wherein the formation of the metal films by chemical vapor deposition technique is carried out in two steps, with the deposition temperature of the second step being set to be higher than the deposition temperature of the first step, whereby a via hole or a wiring groove can be embedded without the formation of voids. As a result a highly reliable wiring can be achieved even on a fine LSI.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: January 16, 2001
    Assignee: NEC Corporation
    Inventor: Kazumi Sugai