Patents Represented by Attorney Haynes Beffel & Woldfeld LLP
  • Patent number: 8146047
    Abstract: An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed for alternative implementations of the circuit, and used to identify an alternative more likely to meet timing constraints.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: March 27, 2012
    Assignee: Synopsys, Inc.
    Inventors: Brent Gregory, William C. Naylor, Jr., Bogdan Craciun
  • Patent number: 7163842
    Abstract: A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-up configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: January 16, 2007
    Assignee: Chip Pac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: D520884
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: May 16, 2006
    Assignee: Tim Simon, Inc.
    Inventors: Timothy M. Simon, Matthew T. Fisher