Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an on chip reprogrammable instruction set accelerator RISA. Reprogrammable execution units may be made using field programmable gate array technology having configuration stores. Techniques for translating a computer program into executable code relying on the RISA involve providing a library of defined and programmed instructions, and compiling a program using the library to produce an executable version of the program using both defined and programmed instructions. The executable version can be optimized to conserve configuration resources for the programmable execution unit, or to optimize speed of execution.