Abstract: A method and apparatus for cached adaptive transforms for compressing data streams, computing similarity, and recognizing patterns have been disclosed. In one embodiment of the invention an encoder and decoder begin with a baseline transform. As data is transferred an algorithm is arranged so that the encoder and decoder adapt toward a superior basis than the baseline, with a corresponding reduction in the encoding bit rate. That is the algorithm adapts to the incoming data stream and can use a custom basis. We deliberately avoid having to send the custom basis itself (when possible), because sending the basis vectors consumes precious bandwidth and may defeat the goal of compression. The encoder and decoder can bootstrap themselves into using one or more better bases. In one embodiment of the invention there is no beginning baseline transform shared between the encoder and the decoder.
Abstract: A method and apparatus for pre-clocking have been disclosed. In one case pre-clocking is used to effectively decrease the delay to output timing with respect to a clock. In another case pre-clocking is used to allow an output signal more time to reach a given level. In another case a pre-clocking adjustment may be determined while a device is in operation.
Abstract: A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such.
Type:
Grant
Filed:
December 29, 2006
Date of Patent:
October 13, 2009
Assignee:
Integrated Device Technology, Inc.
Inventors:
Frank Hwang, Howard Yang, Chuen-Der Lien, Jimmy Lee