Abstract: A method for minimizing cycle time to improve machine performance is described. The approach prioritizes placement and partitioning decisions based on the criticality of paths and their constituent net segments. It provides an initial coarse approximation to a final more optimum configuration by iteratively improving on it through the use of deterministic techniques. The method optimizes placement by means of heuristic algorithms that are based on a cost function that is dependent on net segment and path criticality.

Abstract: A variable self-correcting on-chip circuit comprised of a plurality of digital circuit components is described, whereby electrical signals are precisely positioned with respect to one another. Electrical signals are converted into a number of pulses within a predefined time window. A first number of pulses obtained from free on-chip circuit oscillation is compared to a second number of pulses derived from a predetermined delay defined by the user. An unequal comparison generates control signals capable of advancing or retarding electrical signals. The delay adjustments account for technology, process, temperature and power supply variations. The compounded effect of these variations translates into a certain delay for which self-correction takes effect.

Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.

Abstract: A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by .+-.50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.

Abstract: A semiconductor device such as a laser diode grown on a structured substrate surface having horizontal regions and adjacent inclined sidewall surfaces. The horizontal regions are of standard orientation while the inclined surfaces are misoriented. The layers forming the device are grown on top of a structured surface, with at least the active layer of the semiconductor material assuming an ordered state which depends on the orientation of the substrate surface. The center section of the active layer is deposited on top of a horizontal region. This section is in the ordered state and has a lower bandgap energy than the terminating sections which are grown on the inclined regions and which exhibit a wider bandgap. The active layer can be terminated in either lateral direction with wider bandgap materials so that buried devices can be obtained that provide strongly confined and non-absorbing mirrors.