Abstract: A method for correcting error bursts in data which are uncorrectable by an ECC in a communications channel in which no pointer is available or if available is not generated. The data is recorded in blocks preferably comprising subblocks. Parity cell syndromes are generated for each block during writing; and during reading these syndromes are analyzed to identify possible starting points of error burst locations. A trial correction is applied to the data in the uncorrectable block (or subblock), then verified whether successful using CRC. The correction is accepted as valid if and only if only one trial correction is verified as successful. The maximum number B of consecutive bytes in error correctable in a block is less than, the number N of bytes in each parity cell, and N-B is selected to limit the probability of miscorrection.

Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

Abstract: A magnetic storage system in which a magnetoresistive (MR) transducer utilizes a high coercivity magnetic material to produce a bias field for achieving higher signal output with low currents for narrow track width applications. Strips of high coercivity magnetic material contiguously contact opposite track-overlying edges of an MR layer. Each strip has a horizontal component of magnetization times its thickness that is at least equal to a horizontal component of magnetization of the MR layer times its thickness before the MR layer is biased by the strips, and each strip has its magnetization direction canted at an angle .phi. from its horizontal component. The MR layer is asymmetrically positioned between spaced magnetic shields and the MR layer is separated by a conductive nonmagnetic spacer layer from a shunt layer.

Abstract: A data processing system and method providing error protection for data transmitted between a processor and a buffer in one data format and transmitted between the buffer and a user device in a different data format. An adaptor is interposed between the processor and the buffer for transmitting to the buffer (i) successive data segments in the one data format, each ending with appended check bytes in a preselected cyclic redundancy code (CRC); and (ii) check bytes using the same CRC appended at the end of each segment in the different data format to create in the buffer records which are a composite of both formats, but viewed as in the one data format by the processor and as in the different data format by the user device. The boundaries of the segments in each format must be known to the adaptor. Since both formats use the same CRC, CRC bytes for each segment in each data format will provide an identical preselected value in the absence of a detectable error.

Abstract: An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.

Abstract: Apparatus and method for transmitting spectral null sequences of a spectrally-constrained code over a partial response channel. A Viterbi detector receives the sequences from the channel and has a time-varying detector trellis structure derived from a running-digital-sum (RDS) trellis structure that requires each one of a set of quasicatastrophic sequences to be generated only from a trellis state corresponding to a respective preselected unique RDS value.

Abstract: A magnetoresistive (MR) sensing system comprises an MR sensor with a layered spin valve structure including thin first and second layers of ferromagnetic material separated by a thin layer of nonmagnetic metallic material. The magnetization direction of the first layer at a zero applied magnetic field is substantially parallel to the longitudinal dimension of the MR sensor and substantially perpendicular to the fixed or "pinned" magnetization direction of the second layer. A thin keeper layer of ferromagnetic material is separated by a thin spacer layer from the layered spin valve structure. This keeper layer has a fixed magnetization direction substantially opposite that of the second layer and a moment-thickness product substantially equal to that of the second layer for cancelling the magnetostatic field from the second layer.

Abstract: Maximum likelihood detection of a trellis code using a Viterbi detector constructed from a time-varying trellis structure that is associated with a partial response channel and consists of connected trellises with periodically repeated patterns of nodes and subtrellises of said trellises. Each subtrellis has nodes representing a current state of the channel and value of a predetermined tracked attribute. A survivor metric and a survivor sequence from a node at the end of one subtrellis are reassigned to a node at the beginning of an adjacent subtrellis having a different value of the tracked attribute for increasing minimum distance properties, reducing error event length and improving code constraints for timing and gain control. The one subtrellis and adjacent subtrellis may be within a single trellis or in adjacent trellises.

Abstract: To improve data detection reliability in a coded maximum likelihood signal processing channel, two counters count the number of times actual values of linear functions of digital sample values corresponding to one and another preselected data patterns are within m units above and m units below, respectively, a preselected decision boundary used to determine whether detected data corresponding to a coded sequence of runlength limited code is a "1" or a "0". A difference count has a magnitude and sign denoting difference between counts in the two counters. After N occurrences of each preselected data pattern irrespective of how far from the boundary, the boundary is adjusted upwardly or downwardly, provided the difference count at least equals +S or at most -S, respectively.

Abstract: A method for constructing trellis codes and an apparatus for providing trellis codes with increased minimum distance between output sequences of partial response channels with constrained inputs. A Viterbi detector expands a conventional trellis structure for the channel incorporating additional states interconnected such that a preselected function associates each state in the trellis with an algebraic evaluation of a polynomial at a particular element of a finite field. The detector trellis is time-varying such that only certain values of the preselected function are allowed every m bits. The time-variation assures that there are no minimum distance extensions of erroneous sequences beyond a predetermined length in the trellis. Reliability of storage channels is desirably increased, because more noise is required to overcome the additional distance and cause an error in distinguishing the correct encoded sequence.

Abstract: A magnetoresistive (MR) read transducer assembly having passive end regions separated by a central active region, and a method of fabricating it. Layers of a first biasing material and a nonmagnetic decoupling spacer material are deposited on a substrate, then covered by a mask only in the central region. By etching or ion milling, those parts of the layers not covered by the mask are removed to define a transverse biasing means in the central region and define the passive end regions. With the same mask remaining in place, a conductive material and exchange layer comprising a second biasing material are deposited over all regions. The mask is removed to define and provide conductor leads and longitudinal biasing means only in the end regions. MR material is thereafter deposited as a continuous thin film in direct contact with the central region containing the transverse biasing means and in direct contact with the end regions containing the longitudinal biasing means.

Abstract: A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.

Abstract: Decoder for processing digital sample values corresponding to an incoming read signal representative of coded binary data. Functional expressions of digital sample values are precomputed for a preselected number of sample values ahead of a current sample value. To provide binary decision outputs, preselected functional expressions are compared against binary representations of corresponding thresholds that are conditioned by the sign of a selected functional expression comprising at least one preselected digital sample value. These outputs, the sign of the selected functional expression, the current value and previous value of decoded data, and the current value of detected phase, are all used to determine the next value of decoded data and next value of detected phase. These next values become the current values of decoded data and detected phase for the next clock cycle.

Abstract: Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.

Abstract: An electrical plug selectively insertable into receptacles having different configurations of apertures for effecting selectable electrical connections. A plurality of contact prongs have extended positions in which they project exteriorly of a housing. Each of an appropriate subset of these prongs is adapted automatically to sense and enter matching apertures of a selected receptacle. The remaining prongs during such entry are moved inward of the housing by contact with and movement relative to a surface of the selected receptacle adjacent to the apertures, and cause prongs of the subset to be locked in their extended positions as they enter the matching apertures.

Abstract: A method and apparatus for encoding and decoding a (t.sub.1,t.sub.2)-skew-tolerant (ST) (t.sub.1 +s.sub.1,t.sub.2 +s.sub.2)-skew-detecting (SD) code, and for correcting and detecting skewed transitions in a parallel asynchronous communication system without acknowledgement, where t.sub.1, t.sub.2, s.sub.1, and s.sub.2 are selectable nonnegative integers. Even though transitions sent at the same time in parallel channels may arrive at different times, a limited degree of variation in transmission speeds is permitted between channels.Assume t.sub.1 is the maximum correctable number and t.sub.1 +s.sub.1 the maximum detectable number of transitions that can be missing from a first transmitted codeword when the first transition arrives from a second transmitted codeword, and t.sub.2 is the maximum correctable number and t.sub.2 +s.sub.2 the maximum detectable number of transitions from the second codeword that can arrive before the last transition of the first codeword arrives.

Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array.

Abstract: A memory controller performs parity encoding on a plurality of data strings moving between a memory connected via a read path to a data bus connected to a corresponding plurality of storage devices. A write buffer has one input for receiving data for storage in the memory and another input for receiving data from the memory for parity calculation. Two outputs of the write buffer are connected to a parity generator. Circuitry responsive to control signals from the data bus conditions the parity generator to logically and recursively combine the two outputs of the write buffer for supplying an updated parity calculation to the memory via a write path. To provide error detection and correction an ECC generator is interposed between the write path and the parity generator, and an ECC check/correction unit is interposed between the read path and control-signal-responsive circuity. The parity encoding is performed using a code that is associative and commutative.

Abstract: A plurality of noncontiguous polygonal regions of phase-shifting material have edges spaced apart less than the distance at which images of said edges would separate. The edges of the regions of phase-shifting material have differing arbitrarily selectable angular orientations (nonparallel as well as parallel) on a nonphase-shifting material. The noncontiguous phase-shifting regions may be arranged in a matrix of parallel columns and rows to facilitate fabrication and facilitate writing of the phase-shifting regions in any arbitrary pattern on an image plane. At least one of the phase-shifting regions constitutes a connective phase-shifting region with edges spaced from edges of adjacent ones of the phase-shifting regions to create a pattern with a continuous body of photoresist covering areas corresponding to the phase-shifting regions upon exposure of the mask.

Abstract: A nonvolatile magnetoresistive (MR) storage device comprising a plurality of MR storage elements, each comprising a substrate and a multilayered structure including two thin film layers of ferromagnetic material separated by a thin layer of nonmagnetic metallic conducting material. The magnetization easy axis of both ferromagnetic layers in each storage element is oriented substantially lengthwise of the storage elements and substantially parallel to the direction of an applied sense current. The magnetization direction of one of the ferromagnetic layers is fixed in a direction substantially lengthwise of the storage elements, and the magnetization direction of the other layer is free to switch between two digital states in which the magnetization is substantially parallel or substantially antiparallel to the magnetization direction in the one layer.