Patents Represented by Law Firm Hickman and King
  • Patent number: 5200809
    Abstract: A technique for packaging an integrated-circuit die in a conventional molded-plastic package exposes the lead frame to which the integrated-circuit die is attached so that heat-conducting columns can be directly attached to the leadframe through vias formed in the molded plastic package. The vias expose selected areas of the lead-frame to which are attached the thermally conductive columns, which extend to an exterior surface of the molded plastic package so that the lead-frame and the conductive columns provide a path for conduction of heat from the die to the exterior of the package.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: April 6, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5172471
    Abstract: A CMOS integrated circuit assembly for providing reduced power supply and ground inductances has a first conducting layer which is formed over an insulating layer formed on top of the integrated-circuit chip. The first conducting layer is connected to wire bond pads which are wirebonded to a package. This first conducting layer forms a single, low-inductance conductor for a VDD supply voltage and extends over a substantial area so that it has an inductance significantly less than the inductance of a conventional conductor. A second conducting layer is forms a low-inductance VSS conductor. Power can be selectively distributed through conductive layers of this to provide power supply isolation between selected circuits of the integrated circuit.
    Type: Grant
    Filed: June 21, 1991
    Date of Patent: December 22, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Chin C. Huang
  • Patent number: 5159374
    Abstract: During development of photoresist on the frontside of a semiconductor wafer, developer solution is prevented from contaminating the backside of a wafer by using a film of de-ionized water to seal the backside. The wafer is mounted to a vacuum chuck, which is in contact with the backside of the wafer. A ring member having a top surface is positioned adjacent to the backside of the wafer mounted to the vacuum-chuck. The film of de-ionized water is formed between the backside of the wafer and the ring so that the film of deionized water provides a seal to prevent developer solution from being drawn by vacuum pressure to the area on the backside of the wafer which is adjacent to the vacuum chuck. To aid in formation of the water sealing ring, the top surface of the ring if formed of a non-wetting material and a circular groove is formed in the top surface. A housing from which the ring projects provides a shield for developer solution.
    Type: Grant
    Filed: April 4, 1991
    Date of Patent: October 27, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Gary W. Groshong
  • Patent number: 5159266
    Abstract: A test socket and a method is provided for mounting and testing a quad flat pack QFP integrated-circuit package, where the QFP package has its leads cut to extend a predetermined distance from the sidewalls of the QFP integrated circuit package. The test socket includes a base to which are mounted a number of resilient contact blades having contacts for contacting the cut leads of the QFP device. A number of tester connection pins are mounted in the base and are connected to the contact blades. A movable comb member spaces the contact blades apart and is adjustably positioned to urge the contact blades into contact with the cut leads of a QFP device.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: October 27, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Brian M. Appold
  • Patent number: 5142844
    Abstract: A horizontal force moves a tape-automated-bonded (TAB) carrier along a first horizontal surface so that the leading edge of the TAB carrier is elevated above a second horizontal surface located beneath the open bottom area of the stacking magazine. After the center of gravity of the TAB carrier has passed a pivot line, the TAB carrier is pivoted about the pivot line by the force of gravity and assumes a horizontal position within the open bottom area of the stacking magazine. If the stacking magazine contains one or more previously-loaded TAB carriers, the TAB carrier being inserted into the open bottom area of the stacking magazine pushes upwardly against the lower surface of the lowest previously loaded TAB carrier so that the weight of the one or more previously loaded TAB carriers also helps to pivot the TAB carrier being loaded about the pivot line.
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: September 1, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Ronald E. Frye, Jr.
  • Patent number: 5134316
    Abstract: A buffer with reduced output swing characterized by a CMOS logic level compatible input, an output adapted to develop a reduced voltage swing output signal, and a precharged converter circuit coupled between the output and the input for converting the input signal to the output signal. The precharged converter circuit includes a voltage range conversion stage coupling the input to the output of the buffer and a precharger stage coupled to the voltage range conversion stage to provide the voltage range conversion stage with a ready supply of charge to quickly change the output signal in response to a change in the input signal. A method for reducing output swing on a buffer includes precharging a voltage range conversion circuit capable of developing an output signal which is variable within an output range and coupling the conversion circuit to an input signal which is variable within an input range which is larger than the output range.
    Type: Grant
    Filed: December 12, 1990
    Date of Patent: July 28, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Paul D. Ta