Patents Represented by Law Firm Hickman Beyer & Weaver
  • Patent number: 5621817
    Abstract: An apparatus for recognizing shapes characterized by a stroke grouper receptive to a plurality of strokes formed on a screen of a pen-based computer system; a shape recognition engine receptive to a stroke group produced by the stroke grouper; and a knowledge base coupled to the shape recognition engine, where the knowledge base includes, at a minimum, knowledge concerning closed polygons and closed curves. Preferably, the closed curves of the knowledge base include both circles and ellipses. A method for recognizing digitized shapes in a computer system includes the steps of receiving at least one user-initiated stroke; grouping the user-initiated stroke with related strokes to form a stroke group; and analyzing the stroke group to make a best-guess shape represented by the stroke group. Preferably, the method also looks for other shapes which are related to the best-guess shape and modifying at least one of the location, size, or shape of the best-guess shape to conform with the other shapes.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: April 15, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Radmilo Bozinovic, Giulia Pagallo
  • Patent number: 5621876
    Abstract: A method of modifying a display matrix in a matrix display area in a window on a computer display screen. The method includes the steps of displaying data in a matrix format, thereby forming a display matrix in the matrix display area, the matrix display area having a first dimension, and increasing, responsive to a selection of an increase activator, the number of existing columns of matrix cells in the display matrix by adding an additional column of matrix cells to the display matrix. The method further includes the step of computing, using a central processing unit, a computed width of a column of matrix cells in the existing columns of matrix cells if the column of matrix cells is reduced in width to accommodate the additional column of matrix cells.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: April 15, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Seth T. Odam, James R. Harker, Joseph G. Ansanelli, John L. Welde, Jr.
  • Patent number: 5620928
    Abstract: A method of manufacturing an integrated circuit package assembly including (i) an integrated circuit die having a bottom surface and a plurality of input/output terminals, (ii) electrically conductive traces and/or contacts accessible from outside the assembly, and (iii) an encapsulating material encapsulating the integrated circuit die and portions of the electrically conductive traces and/or contacts will be disclosed. The method includes the following steps. First, a temporary support substrate or carrier having a top surface is provided for supporting the integrated circuit package as the package is being assembled. Then, the integrated circuit die is detachably supported on the top surface of the temporary support substrate. Each of the input/output terminals on the integrated circuit die are electrically connected to the electrically conductive traces and/or contacts.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: April 15, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Shaw W. Lee, Anthony E. Panczak, Jagdish G. Belani
  • Patent number: 5619698
    Abstract: The present invention discloses a variety of methods and apparatus for providing patches within a computer operating system. A patch structure in accordance with one embodiment of the present invention includes a patch block which serves to link the patch structure into a patch chain, and a patch which contains the desired functionality of the patch structure. The patch chain includes a root patch structure and a final patch structure. The root patch structure has a root patch block and a given function which has the root functionality.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: April 8, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Alan W. Lillich, Jeffrey R. Cobb, Erik L. Eidt, Wayne N. Meretsky
  • Patent number: 5618356
    Abstract: In a zirconium-alloy fuel element cladding, a method for generating regions of coarse and fine intermetallic precipitates across the cladding wall is provided. The method includes steps of specific heat treatments and anneals that coarsen precipitates in the bulk of the cladding. The method also includes at least one step in which an outer region (exterior) of the cladding is heated to the beta or alpha plus beta phase, while an inner region (interior) is maintained at a temperature at which little or no metallurgical change occurs. This method produces a composite cladding in which the outer region comprises fine precipitates and the inner region comprises coarse precipitates.
    Type: Grant
    Filed: June 12, 1995
    Date of Patent: April 8, 1997
    Assignee: General Electric Company
    Inventors: Ronald B. Adamson, Gerald A. Potts
  • Patent number: 5619163
    Abstract: A bandgap voltage reference includes a series connection of a proportional-to-absolute-temperature (PTAT) voltage drop resistor with a V.sub.BE voltage drop transistor, such that a bandgap voltage V.sub.REF =V.sub.PTAT +V.sub.BE can be developed across the series connection. The bandgap voltage reference further includes a PTAT current generator having a pair of bipolar transistors which derive their base currents from a base current node between the PTAT voltage drop resistor and the V.sub.BE voltage drop transistor. The PTAT current developed by the PTAT current generator is compensated to counteract the effect of the base currents flowing through the PTAT voltage drop resistor.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: April 8, 1997
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Ronald B. Koo
  • Patent number: 5618757
    Abstract: Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: April 8, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Subhas Bothra, Milind G. Weling
  • Patent number: 5616392
    Abstract: A buffet platter with a plastic frame for maintaining the space between buffet platters stacked on each other has a smooth-surfaced, preferably mirrored, food-carrying plate at the upper side is surrounded by the plastic frame, which is profiled at the outer edge to engage with a buffet platter of the same design stacked thereon, in order to prevent sideways slipping. The plastic frame is formed in one piece and the food-carrying plate is supported on a base surface of the plastic frame that is formed in one piece with the plastics frame.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: April 1, 1997
    Inventor: Georg Treutwein
  • Patent number: 5617297
    Abstract: A portable peripheral card for an electrical device is disclosed that has an injected molded housing package. In one aspect of the invention, the peripheral card has a printed circuit board, a female electrical connector, and a solid one-piece injected molded package, whereas the molding compound includes organic polymer fibers. The printed circuit board has electrical components mounted thereon and the female electrical connector is attached to the printed circuit board to permit communications between the electrical components on the printed circuit board and the electrical device. The solid one-piece package encapsulates the printed circuit board and the electrical components yet exposes a portion of the electrical connector to facilitate electrical connections between the printed circuit board and the electrical device. In one preferred embodiment, the organic polymer fibers includes at least one selected from the group consisting of cotton, cellulose, polyester and nylon.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: April 1, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Randy Lo, Hem P. Takiar
  • Patent number: 5615357
    Abstract: A method of adapting execution-driven simulators to accept traces is provided. First, a benchmark program is executed to provide a trace file of the executed instructions. Each output instruction of the trace file includes the program counter (PC) and the op code of the instruction executed. In addition for memory access instructions, the trace file includes effective memory addresses, and for decision control transfer instructions, the trace file includes actual branch destinations. Next, the trace file is randomly sampled to produce relatively small segments of contiguous trace instructions. These are then provided to a processor model which processes them concurrently with the benchmark program which is provided in a memory model connected to the processor model. To ensure that the processor design performance is accurately predicted, the trace file effective addresses are used during execution.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: March 25, 1997
    Assignee: Sun Microsystems, Inc.
    Inventor: Loran P. Ball
  • Patent number: 5614437
    Abstract: A method for manufacturing an ohmic contact on a semiconductor device, as disclosed herein, includes a first step of etching a via through a non-conductive layer formed over a partially fabricated version of the semiconductor device. This step exposes a region of a device element such as a source, gate electrode, etc. Next, an ohmic contact layer including tantalum and silicon is deposited over the partially fabricated device and in the vias by sputtering in an argon atmosphere. Thereafter, and in the same processing apparatus, a barrier layer including a tantalum silicon nitride is deposited over the ohmic contact layer. Then an aluminum alloy metallization layer is directly deposited on the partially fabricated device at a temperature of at least 650.degree. C. At this deposition temperature, the metallization layer conformally fills the via, thereby producing a stable, uniform contact.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: March 25, 1997
    Assignee: LSI Logic Corporation
    Inventor: Ratan K. Choudhury
  • Patent number: 5615347
    Abstract: A method and apparatus for linking GUI sliders displayed on a computer screen. A master slider and a slave slider are displayed, each including a knob and a guide. The master knob can be moved along the master guide in response to input from a user, such as with a pointing device. The movement of the slave knob of the slave slider is influenced along the slave guide based on the position and/or movement of the master knob. The slave slider can preferably be in a full slave mode or in a partial slave mode. In full slave mode, the slave knob tracks the movement of its master knob and cannot be selected directly by the user. In partial slave mode, a slave knob can be directly selected and moved by the user, but includes a limit to its movement based on the master knob's current position. Graphical indications of the limits and/or influence on the slave slider are displayed, such as half tone displays on the screen and lines indicating the limits to movement.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: March 25, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Lisa L. Davis, Susan M. Bartalo, James L. Mensch, Mark C. Pontarelli, Robert E. Snow, Jr.
  • Patent number: 5615285
    Abstract: A method for the angle-independent recognition of handwritten objects including: a) receiving a handwritten stroke; b) normalizing the stroke; c) matching the normalized stroke against a stroke database to obtain at least one character part interpretation; and d) recognizing a handwritten object using one or more of the character part interpretations. Preferably, the step of normalizing the stroke includes the step of normalizing an angle of the stroke by first determining a stroke angle and then rotating the stroke by the stroke angle until the stroke is at a normalized position.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 25, 1997
    Assignee: Apple Computer, Inc.
    Inventor: Ernest H. Beernink
  • Patent number: 5614868
    Abstract: A phase locked loop including a VCO having a multi-stage oscillator portion and a combinational logic portion. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of a VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency, with one of such clock phases used in the determination of the VCO control signal. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: March 25, 1997
    Assignee: VLSI Technology, Inc.
    Inventor: Edward T. Nielson
  • Patent number: 5614249
    Abstract: A chemical vapor deposition apparatus includes a gas manifold having a first gas flow port through which a gas flow path extends, and a first peripheral surface which extends about the first gas flow port. The chemical vapor deposition apparatus further includes a second gas flow port through which the gas flow path extends, and a second peripheral surface extending about the second gas flow port. A connection of the gas manifold is provided such that the first and second peripheral surfaces substantially mutually engage intended for providing a substantial seal of the gas flow path. A groove is provided in at least one of the first and second peripheral surfaces and extends so as to communicate with at least one of the first and second gas flow ports. The groove facilitates flow of a test gas therein from outside the chemical vapor deposition apparatus towards the respective gas flow port.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: March 25, 1997
    Assignee: LSI Logic Corporation
    Inventor: Mark I. Mayeda
  • Patent number: 5612719
    Abstract: A gesture sensitive button for graphical user interfaces characterized by a digital computer, a screen coupled to the digital computer, a pointer mechanism used for pointing locations on the screen, a "button" image displayed on the screen, and a gesture recognizer for detecting gestures made on the screen by the pointing mechanism. The button is responsive to at least two different button gestures made on the screen on or near the button. A process implementing the gesture sensitive button of the present invention includes: providing a button image on a computer screen; detecting a gesture made on the screen by a pointer such as a stylus, mouse, or trackball; determining whether the gesture is associated with the button image; and initiating one of at least two processes if the gesture is associated with the button image. The gesture sensitive button conserves real estate on the computer screen by permitting a single button to control multiple functions and processes.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: March 18, 1997
    Assignee: Apple Computer, Inc.
    Inventors: Ernest H. Beernink, Gregg S. Foster, Stephen P. Capps
  • Patent number: 5611478
    Abstract: A lead frame clamping arrangement for lead frame/interposer bonding is disclosed that clamps the leads to be bonded at two spaced apart locations with the bonding area being positioned between the clamped portions of the particular leads being bonded. During bonding of a selected lead to its associated trace, a bonding tool tip is positioned in the gap between the clamps. In a preferred embodiment of the invention, the clamping arrangement includes a lead tip clamp and a lead arm clamp. In some embodiments, the lead arm clamp takes the form of a window clamp and the lead tip clamp includes a spring plate positioned within the window such that a channel shaped gap is formed between the spring plate and the window clamp. The gap exposes the bonding regions of all of the leads to be attached to the interposer. With this arrangement, all of the leads of a radially based lead frame can be secured to the interposer without requiring the resetting of the clamp.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: March 18, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Chainarong Asanasavest
  • Patent number: 5609972
    Abstract: A cell pressure control system is disclosed which includes a conductive frangible tab which tears in response to a defined pressure. The frangible tab is affixed at one position to a stationary member and at another position to a deflection member which deflects in response to increasing internal cell pressure. When the cell pressure increases to a dangerous level, the deflection member exerts sufficient pressure on the frangible tab to cause it to break. When the tab breaks, the cell goes to open circuit, thus reducing the danger of continued pressure build up. If the cell's internal pressure continues to increase even after the pressure contact is opened, a second stage of the pressure control mechanism may be activated. Specifically, a pressure rupturable region in the above-mentioned deflection member will rupture and release the cell's internal pressure.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: March 11, 1997
    Assignee: PolyStor Corporation
    Inventors: James L. Kaschmitter, Frank L. Martucci, Steven T. Mayer, Jung H. Souh, Sean Thompson
  • Patent number: 5610843
    Abstract: Apparatuses and methods for implementing a controller in a system having a plurality of sensors and a plurality of actuators. In one embodiment, the inventive method includes the steps of measuring a transfer function P, the measured transfer function P representing a neutralization path in a Q-parameterized version of the controller, and designing a transfer function Q, the designed transfer function Q representing the feed forward path in the Q-parameterized version of the controller. The invention further includes the step of sparsifying both the transfer functions P and Q for a given accuracy threshold using wavelet transforms, thereby forming transfer functions Ps and Qs respectively for implementing the controller.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: March 11, 1997
    Assignee: SRI International
    Inventor: Kenneth C. Chou
  • Patent number: 5610417
    Abstract: A method for making an integrated circuit characterized by: determining a range of bonding pad pitches which varies between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to the minimum bonding pad pitch; forming a base set including a plurality of drivers having the determined driver pitch; forming customization layers over the base set, where the customization layers include a plurality of bonding pads having a pad pitch greater than the minimum bonding pad pitch but less than or equal to the maximum bonding pad pitch; and coupling some, but not all, of the drivers to the pads. As a result, a single base set can be used to make integrated circuits having a range of bonding pad pitches. The method and structure of the present invention are very well adapted for use in gate array integrated circuits.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: March 11, 1997
    Assignee: VLSI Technology, Inc.
    Inventor: Bryan C. Doi