Patents Represented by Attorney, Agent or Law Firm Hitt Gaines & Boisbrun
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Patent number: 6904586Abstract: An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.Type: GrantFiled: March 25, 2002Date of Patent: June 7, 2005Assignee: LSI Logic CorporationInventors: Majid Bemanian, William D. Scharf, Bruce L. Entin
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Patent number: 6813704Abstract: For use in an instruction queue having a plurality of instruction slots, a mechanism for queueing and retiring instructions. In one embodiment, the mechanism includes a plurality of tag fields corresponding to the plurality of instruction slots, and control logic, coupled to the tag fields, that assigns tags to the tag fields to denote an order of instructions in the instruction slots. In addition, the mechanism includes a tag multiplexer, coupled to the control logic, that changes the order by reassigning only the tags.Type: GrantFiled: December 20, 2001Date of Patent: November 2, 2004Assignee: LSI Logic CorporationInventor: Hung T. Nguyen
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Patent number: 6745314Abstract: A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes: (1) address calculation logic, having multiple datapaths, that calculates, from data regarding a buffer operation, an updated address result therefor and (2) modification order determination circuitry, coupled in parallel with the address calculation logic, that transmits a memory access request and the updated address result in an order that is based on whether the buffer operation is pre-modified or post-modified.Type: GrantFiled: November 26, 2001Date of Patent: June 1, 2004Assignee: LSI Logic CorporationInventor: Shannon A. Wichman
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Patent number: 6727332Abstract: Use of isotactic polypropylene homopolymers or copolymers in processes in which the polypropylene solidifies from a melt, wherein for enhanced speed of solidification of the polypropylene the polypropylene has a melt temperature and a crystallisation temperature not more than 50° C. less than the melt temperature resulting from the polypropylene having been produced using a metallocene catalyst component having the general formula: R″(CpR1R2R3)(Cp′Rn′)MQ2. Cp and Cp′ are a substituted cyclopentadienyl ring, and a sybstituted or unsubstituted fluorenyl ring, respectively. R″ is a structural bridge; R1 is a substituent on the cyclopentadienyl ring distal to the bridge. The distal substituent comprises a bulky group of the formula XR*a; X is chosen from Group IVA. M is a Group IVB transition metal or vanadium and each Q is hydrocarbyl having 1 to 20 carbon atoms or is a halogen.Type: GrantFiled: August 24, 2001Date of Patent: April 27, 2004Assignee: Atofina Research S.A.Inventor: Axel Demain
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Patent number: 6653431Abstract: Use of a catalyst system comprising a metallocene catalyst component of general formula R″ (CpRn)(Cp′R′n)MQ2 supported on an inert support in the slurry phase production of linear low density polyolefin, wherein Cp is a cyclopentadienyl moiety, Cp′ is a substituted or unsubstituted fluorenyl ring: R″ is a structural bridge imparting stereorigidity to the component; each R is independently hydrogen or hydrocarbyl having 1 to 20 carbon atoms in which 0≦m≦4; each R′ is independently hydrocarbyl having 1 to 20 carbon atoms in which 0≦n≦8; M is a Group IVB transition metal or vanadium; and each Q is hydrocarbyl having 1 to 20 carbon atoms or halogen; the metallocene having a centroid-M-centroid angle in the range 105° to 125°.Type: GrantFiled: March 22, 2002Date of Patent: November 25, 2003Assignee: Fina Research, S.A.Inventors: Abbas Razavi, Liliane Peters
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Patent number: 6630546Abstract: Use of a catalyst system comprising a metallocene catalyst component of general formula R″(CpRm) (Cp′R′n)MQ2 supported on an inert support in the slurry phase production of linear low density polyolefin, wherein Cp is a cyclopentadienyl moiety, Cp′ is a substituted or unsubstituted fluorenyl ring; R″ is a structural bridge imparting stereorigidity to the component; each R is independently hydrogen or hydrocarbyl having 1 to 20 carbon atoms in which 0≦m≦4; each R′ is independently hydrocarbyl having 1 to 20 carbon atoms in which 0≦n≦B; M is a Group IVB transition metal or vanadium; and each Q is hydrocarbyl having 1 to 20 carbon atoms or halogen; the metallocene having a centroid-M-centroid angle in the range 105° to 125°.Type: GrantFiled: March 22, 2002Date of Patent: October 7, 2003Assignee: Fina Research, S.A.Inventors: Abbas Razavi, Liliane Peters
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Patent number: 6593678Abstract: An element of a SAW filter network, a method of filtering a signal and a SAW filter network incorporating the element or the method. In one embodiment, the element includes: (1) a SAW resonator having a nominal usable bandwidth and (2) an extrinsic capacitor coupled in parallel with the SAW resonator, the extrinsic capacitor interacting with the SAW resonator to cause an anti-resonance frequency of the element to move toward a resonance frequency thereof and thereby decrease an overall operating bandwidth of the element.Type: GrantFiled: October 24, 2000Date of Patent: July 15, 2003Assignee: Clarisay, Inc.Inventor: James E. Flowers
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Patent number: 6591291Abstract: A system for, and method of, generating an alias source address for an electronic mail (“e-mail”) message having a real source address and a destination address and a computer network, such as the Internet, including the system or the method. In one embodiment, the system includes an alias source address generator that employs the destination address to generate the alias source address. The system further includes an alias source address substitutor that substitutes the alias source address for the real source address. This removes the real source address from the e-mail message and thereby renders the sender, located at the real source address, anonymous. Further-described are systems and methods for forwarding reply e-mail and filtering reply e-mail based on alias source address.Type: GrantFiled: March 12, 1998Date of Patent: July 8, 2003Assignee: Lucent Technologies Inc.Inventors: Eran Gabber, Phillip B. Gibbons, David Morris Kristol, Yossi Matias, Alain J. Mayer
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Patent number: 6585884Abstract: The present invention provides a method of producing a synthesis gas from a regeneration of spent cracking catalyst. The method includes introducing a spent cracking catalyst into a first regeneration zone in a presence of a first oxygen and carbon dioxide atmosphere and at a first regeneration temperature. For example, a temperature that does not exceed about 1400° F., and more preferable a temperature that ranges from about 1150° F. to about 1400° F., may be used as the first regeneration temperature. The method further includes introducing the spent cracking catalyst from the first regeneration zone into a second regeneration zone in a presence of a second oxygen and carbon dioxide atmosphere, and producing a synthesis gas from cracking deposits located on the spent cracking catalyst within the second regeneration zone at a second regeneration temperature substantially greater than said first regeneration temperature.Type: GrantFiled: October 17, 2002Date of Patent: July 1, 2003Inventor: Warden W. Mayes, Jr.
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Patent number: 6579604Abstract: The present invention is directed, in general, to an improved material and method of planarizing a surface on a semiconductor wafer and, more specifically, to a method of altering the properties of polymers, preferably thermoplastic foam polymers, used in polishing applications. The chemical and mechanical properties thermoplastic foam substrates can be transformed by inorganic, inorganic-organic, and or organic—organic grafting techniques, such that the polymer foam is endowed with new set of properties that more desirable and suitable for polishing.Type: GrantFiled: November 27, 2001Date of Patent: June 17, 2003Assignee: PsiloQuest Inc.Inventors: Yaw S. Obeng, Edward M. Yokley
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Patent number: 6575823Abstract: The present invention is directed, in general, to polishing pads for chemical mechanical polishing of semiconductor wafers and integrated circuits. More specifically, the invention is directed to polishing pads containing a precursor slurry modifier. In the presence of a polishing slurry during chemical mechanical polishing, the precursor is released to the polishing slurry to form a slurry modifier thereby improving polishing.Type: GrantFiled: March 4, 2002Date of Patent: June 10, 2003Assignee: PsiloQuest Inc.Inventors: Yaw S. Obeng, Edward M. Yokley
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Patent number: 6568529Abstract: To address the deficiencies of the prior art, the present invention provides a nestable cosmetic package assembly. The nestable package assembly includes at least two cosmetic-containing portions that may be interconnected to provide a convenient, portable, and economical package for cosmetics.Type: GrantFiled: June 29, 2001Date of Patent: May 27, 2003Inventor: Stefani McMurrey
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System and method for orienting seismic energy receivers to yield discriminated vertical shear waves
Patent number: 6564150Abstract: A system for, and method of, orienting seismic energy sources and seismic energy receivers to substantially separate a compressional wave from a vertical shear wave. The method includes reflecting a seismic energy from a subsurface interface to produce a reflected seismic energy wave that has a compressional energy and vertical shear energy associated therewith. A first seismic energy receiver is oriented such that it is aligned with an angle of emergence of the reflected seismic energy wave to thereby maximize the vertical shear energy received by a second seismic energy receiver.Type: GrantFiled: February 20, 2001Date of Patent: May 13, 2003Assignees: Board of Regents for the University of Texas, Vecta Technologies, LPInventors: Allen L. Gilmer, Bob A. Hardage, James L. Simmons, Jr. -
Patent number: 6556921Abstract: The present invention provides a system for, and method of determining vertical fractures in a stratum using scattered horizontal shear and vertical shear modes. The method may include segregating first order horizontal and vertical shear modes of a seismic energy wave into second order horizontal and vertical shear modes, defining a seismic energy wave corridor along a radial path between a seismic energy source and seismic receivers, and gathering seismic data received by the seismic receivers within the corridor, the data including the second order horizontal and vertical shear modes.Type: GrantFiled: September 17, 2001Date of Patent: April 29, 2003Assignee: Board of Regents for the University of Texas SystemInventors: Bob Hardage, Robert J. Graebner
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Patent number: 6552572Abstract: A clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.Type: GrantFiled: October 24, 2001Date of Patent: April 22, 2003Assignee: LSI Logic CorporationInventors: Cyrus C. Cheung, Keith D. Au
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Patent number: 6542686Abstract: The present invention provides an optoelectronic device and a method of manufacture therefor, that prevents dopant diffusion and controls the dopant concentration therein. The optoelectronic device includes an active region formed over a substrate, and an interface barrier layer and barrier layer located over the active region. The optoelectronic device further includes an upper cladding layer located over the interface barrier layer and the barrier layer. In an exemplary embodiment of the invention, the interface barrier layer is an indium phosphide interface barrier layer and the barrier layer is an indium gallium arsenide phosphide barrier layer.Type: GrantFiled: August 25, 2000Date of Patent: April 1, 2003Assignee: Lucent Technologies Inc.Inventors: Michael Geva, Claude Lewis Reynolds, Jr., Lawrence E. Smith
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Patent number: 6535729Abstract: A system for, and method of, processing a wireless file in a computer network and a communications infrastructure incorporating the system or the method. In one embodiment, the system includes: (1) an examiner that receives at least a portion of the wireless file and identifies a filename thereof and (2) a file processor that modifies a content of the wireless file based on the filename.Type: GrantFiled: May 20, 1998Date of Patent: March 18, 2003Assignee: Lucent Technologies Inc.Inventor: Nitin J. Shah
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Patent number: 6528389Abstract: This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material.Type: GrantFiled: December 17, 1998Date of Patent: March 4, 2003Assignee: LSI Logic CorporationInventors: Derryl D. J. Allman, John W. Gregory
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Patent number: 6528845Abstract: The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.Type: GrantFiled: July 14, 2000Date of Patent: March 4, 2003Assignee: Lucent Technologies Inc.Inventors: Jeffrey D. Bude, Richard J. McPartland, Ranbir Singh
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Patent number: D476586Type: GrantFiled: September 10, 2002Date of Patent: July 1, 2003Assignee: Crowd Creaters, Inc.Inventor: Richard H. Nash