Abstract: Provided is an apparatus and method for use thereof. The apparatus, in one embodiment, includes first and second 1×N couplers integrated on a substrate and configured to receive an optical symbol having an intended time slot, N being at least three. The apparatus, in this embodiment, further includes N waveguide arms integrated on the substrate, having modulators and coupled between the first and second 1×N couplers. The apparatus, in this embodiment, additionally, includes a modulator controller configured to drive the modulators such that, following transmission over a distance, components of the optical symbol outside of the intended time slot are attenuated relative to components within the intended time slot.
Abstract: A time division media access controller for use with a multi-port data switch and a method of controlling media access. In one embodiment, the time division media access controller includes a time division receive engine, a time division transmit engine and a time division arbiter coupled to the time division receive and transmit engines. The time division receive engine accepts data from a plurality of data ports and the time division transmit engine provides data to a plurality of data ports. The time division arbiter controls states of the time division receive and transmit engines based on throughput requirements of the data. In preferred embodiments, the time division media access controller complies with the IEEE 802.3 ethernet standard.
Abstract: The present invention provides an application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the application specific integrated circuit includes a programmable logic core having an array of dynamically configurable arithmetic logic units. This particular embodiment further includes a network interface subsystem that includes a media access controller. The network interface is configured to employ a first portion of the programmable logic core that interfaces with the media access controller and that is configurable to process control data. This embodiment further includes a data transmission subsystem associated with a memory device, and configured to employ a second portion of the programmable logic core that stores received data from the network interface subsystem to the memory device and sends transmission data from the memory device to the network interface subsystem in response to an instruction from a host system.
Type:
Grant
Filed:
May 8, 2001
Date of Patent:
May 9, 2006
Assignee:
LSI Logic Corporation
Inventors:
Theodore F. Vaida, Rajiv K. Singh, Peter Gasperini