Patents Represented by Attorney, Agent or Law Firm Holland & Knight LLC
  • Patent number: 6722557
    Abstract: An effective method for cleaning flux residues produced in process of fabricating semiconductor devices, and a method of fabricating the semiconductor devices including this cleaning method are provided. The flux cleaning method for cleaning the solder bump electrodes formed using a flux comprises the steps of: applying a pretreatment process including coating of the solder bump electrode with the flux and applying a heat treatment thereto, and carrying out the flux cleaning to clean the heat-treated flux.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: April 20, 2004
    Inventor: Tohru Tanaka
  • Patent number: 6705516
    Abstract: A historical information recording device provided in a product for storing in a recorder product historical information relating to the product's manufacture, physical distribution, sale, registration, repair, and disposal and transmitting the information in response to information input from the outside, having a plurality of transmission modes and provided with a mode switcher for selecting a first transmission mode at the time of usual use and switching the transmission mode in response to an input signal to a second transmission mode with at least an output, frequency, method of modulation, or transmission time different from that of the first transmission mode, a historical information tamper prevention unit for prohibiting a write operation in the storage unit under predetermined conditions to prevent tampering of the product historical information, and a discriminator for discriminating if the recorder is the specific historical information recorder which should be covered by the recording and/or
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: March 16, 2004
    Inventor: Michitaka Kubota
  • Patent number: 6696309
    Abstract: An electrooptical device including a first substrate including a display section having pixel electrodes and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate is produced as follows. A material layer having a high degree of lattice matching with single-crystal silicon is formed on one face of the first substrate. A polycrystalline or amorphous silicon layer is formed on the first substrate and then a low-melting-point metal layer is formed on or under the silicon layer on the first substrate, or a low-melting-point metal layer containing silicon is formed on the first substrate having the material layer. The silicon layer or the silicon is dissolved into the low-melting-point metal layer by a heat treatment.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: February 24, 2004
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi
  • Patent number: 6693506
    Abstract: A magnetic sticking sheet comprising a non-magnetic base and a magnetic layer formed on the non-magnetic base by coating a magnetic coating material containing ferromagnetic particles and a binder, the magnetic layer having a thickness of 0.03 to 0.10 mm, oriented longitudinally to give a squareness ratio of 80 to 90%, and multipolar-magnetized longitudinally; the sheet having a total thickness of 0.08 to 0.25 mm and flexibility for rolling; the magnetic layer having a surface magnetic flux density of 35 to 100G; and the sheet having a magnetic sticking force, required for removing a magnetic sticking sheet fixed magnetically on a magnetic surface via the magnetic layer while keeping the magnetic surface and the sheet parallel, of 0.4 to 0.9 gf/cm2.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: February 17, 2004
    Inventors: Shinichi Matsumura, Miki Sudo, Kazuto Kawamata, Eiji Ohta
  • Patent number: 6686960
    Abstract: Systems and methods allow driving a solid-state image pickup apparatus at high-speed operation by reducing a number of different samples in the horizontal and vertical directions. In an exemplary embodiment, three or more odd-numbered pixels are incorporated into a single block and signal charges from same color outputs are added within transfer registers such that an average center of the pixels coincides with a pixel at a center of the block. Three transfer electrodes are preferably provided for a column of a vertical transfer register in a part of the vertical transfer register on a side of the horizontal transfer register. The three transfer electrodes may be formed from one layer of three different gate electrode layers. The vertical registers may be arranged in a three column cycle.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: February 3, 2004
    Assignee: Sony Corporation
    Inventor: Tetsuya Iizuka
  • Patent number: 6680801
    Abstract: A minimum frame is set to cover the shape of an opening of each pixel of an optical panel portion, and an intersection between two diagonals of the frame is determined. An X-axis and a Y-axis are set with the intersection between the diagonals taken as a reference point. A ratio between areas, occupied on both sides of the X-axis, of the opening is calculated and a correction amount in the Y-axis direction is calculated on the basis of the area ratio. Similarly, a ratio of areas, occupied on both sides of the Y-axis, of the opening is calculated and a correction amount in the X-axis direction on the basis of the area ratio. The intersection is moved by the correction amounts in the X-axis direction and the Y-axis direction, to obtain plane coordinates. The center position of a micro-lens is aligned to the plane coordinates corresponding to the center of gravity of the opening of the pixel.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: January 20, 2004
    Inventor: Shunji Kurita
  • Patent number: 6681375
    Abstract: A check system for a wiring structure of a printed circuit board for easily calculating an electric energy of a high-speed signal wiring on the printed circuit board and warning when the energy owned by the signal wiring is larger than a designated threshold value. The electric energy radiated from the high-speed signal wiring intended for checking is calculated by using a simple mathematical expression, and a display to identify the signal wiring is outputted when the electric energy owned by the signal wiring is larger than a certain designated threshold value, and also an instructing message to relocate in an internal layer of the circuit board is outputted against the signal wiring.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: January 20, 2004
    Inventors: Kenji Araki, Ayao Yokoyama
  • Patent number: 6672723
    Abstract: The invention provides a liquid crystal projector which can blast an increased amount of cooling air to raise the cooling efficiency without increasing the size of an optical prism unit. The liquid crystal projector includes a dichroic prism, a base for securing the dichroic prism with a lower plate interposed therebetween, a plurality of liquid crystal panel units disposed on side faces of the dichroic prism, and a cooling fan disposed below the base. The base has air holes formed therein such that air current generated by the cooling fan is introduced to the liquid crystal panel units through the air holes to cool the liquid crystal panel units. The lower plate has inclined faces at portions thereof which oppose to the air holes of the base.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: January 6, 2004
    Inventors: Hideki Sugimoto, Shinya Watanabe, Yoshifumi Akaike
  • Patent number: 6670290
    Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: December 30, 2003
    Inventors: Toshiro Kisakibaru, Isao Honbori, Yasushi Kato, Toshikazu Suzuki, Hirohisa Koriyama, Hayato Iwamoto, Hitoshi Abe
  • Patent number: 6664118
    Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising (A) a bit line, (B) a transistor for selection, (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein N≧2 and M≧2, and (D) plate lines in the number of M×N, in which the memory units in the number of N are stacked through an insulating interlayer, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, the first electrodes are in common in each memory unit, and the common first electrode is connected to the bit line through the transistor for selection, and the second electrode of the m-th memory cell in the n-th memory unit is connected to the [(n−1)M+m]-th plate line wherein m=1, 2 . . . M and n=1, 2 . . . N.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: December 16, 2003
    Inventors: Toshiyuki Nishihara, Koji Watanabe
  • Patent number: 6658641
    Abstract: An object of the present invention is to accurately verify errors, etc., in programs when corrections of mask data are carried out by the programs. In order to correct the mask data based on predetermined conditions, a method for mask data verification according to the present invention comprises the steps of preparing corrected mask data by using a plurality of programs each of which has a different algorithm, comparing each of corrected mask data which is prepared in the previous step and as a result of the comparison, if there are differences among the corrected mask data, extracting errors which cause problems as mask data from the differences.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: December 2, 2003
    Inventors: Isao Ashida, Kazuhisa Ogawa
  • Patent number: 6635911
    Abstract: A solid state image sensing device and method of making same. The device includes a sensor portion, a vertical transfer register having a transfer electrode, a shunt interconnection of a refractory metal, and a light shielding film is provided. The shunt interconnection and the light shielding film are insulated from one another with an oxide film, an insulating film to serve as a stopper film at the time of pattering the oxide film is formed under the oxide film and the shunt interconnection, and the oxide film and the insulating film are not provided under the projecting portion of the light shielding film.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 21, 2003
    Assignee: Sony Corporation
    Inventor: Yasushi Maruyama
  • Patent number: 6614111
    Abstract: A semiconductor device able to maintain a bonding state between a bump and an electrode and having high reliability even under thermal stress, wherein a sealing resin is interposed to bond the electrodes and bumps between a wiring board formed with a plurality of electrodes and an IC chip formed with a plurality of bumps, the bumps being formed under the condition that the following formula is satisfied. 100<((&PHgr;A×F)/H)<125 where &PHgr;A represents the top diameter of a bump bonded with an electrode, H the height of a bump projecting from the IC chip and bonded with an electrode, and F the linear thermal expansion coefficient of the sealing resin.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: September 2, 2003
    Assignee: Sony Corporation
    Inventors: Satoshi Iwatsu, Noriyuki Honda
  • Patent number: 6610603
    Abstract: In order to prevent a capacitance element from suffering fluctuation in the capacitance value and deterioration of the reliability caused in the step for planarizing the surface of the substrate after forming the capacitance element, there is provided a process for fabricating a semiconductor device, in which an insulator is formed on a semiconductor substrate; a first wiring layer to be a lower portion electrode; a Ta2O5 layer to be a dielectric film; a second wiring layer to be an upper portion electrode are successively formed; a pattern for the dielectric film and upper portion electrode is formed; a pattern for the lower portion electrode is subsequently formed; an SiN film is formed as a protective film; and planarization is conducted by etching back a spin on glass (SOG).
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: August 26, 2003
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri
  • Patent number: 6608598
    Abstract: An improved tuning method is used in conjunction with a set of nested electrically conducting cones to increase the frequency band over which the resulting radiating system functions as an electrically small antenna with controlled variation in input impedance. This technique enables switching of the frequency band by means of simple circuits that can be activated by a control voltage.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: August 19, 2003
    Inventors: Walter Gee, Paul E. Mayes
  • Patent number: 6602787
    Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: August 5, 2003
    Assignee: Sony Corporation
    Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi
  • Patent number: 6590270
    Abstract: The invention relates to a color solid-state pickup element and a method for producing the same, which can improve the sensitivity by efficiently utilizing light received by the element surface and has an excellent color reappearance property, wherein, in a solid-state pickup element having light receptive elements arrayed and formed on the surface side of a substrate, a light polarizing prism that polarizes light he that has entered from the surface side of the substrate, distributes and irradiates spectral light ha of specified wavelength bands onto a plurality of light receptive areas is provided on the substrate in which the light receptive areas are arrayed and formed; the second light condensing lens that condenses light he irradiated on the surface side of the substrate is provided on the light polarizing prism; an in-layer lens that makes the light hc condensed by the second light condensing lens into a parallel beam hb and causes it to enter the light polarizing prism is provided between the second l
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: July 8, 2003
    Assignee: Sony Corporation
    Inventor: Ryoji Suzuki
  • Patent number: 6586830
    Abstract: An improved semiconductor chip interconnection advantageously employs a thin conductive layer that is used to form conductive members located between two nonconductive layers. The upper nonconductive layer has openings formed therein through which electrical connections are made between contacts in the chip member and the conductive members. The conductive members preferably have portions which are substantially parallel to a bottom surface of the semiconductor chip located between nonconductive layers and an upper nonconductive layer has openings formed therein through which electrical connections are made with the semiconductor chip. The conductive members have portions that extend downward away from the bottom surface of the chip.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: July 1, 2003
    Assignee: Sony Corporation
    Inventor: Takashi Saito
  • Patent number: 6579398
    Abstract: Disclosed is a method of manufacturing an optical waveguide, capable of easily manufacturing an optical waveguide which can hold an excellent light propagating characteristic irrespective of the kind of a supporting substrate. On a transparent substrate, a peelability promoting film obtained by setting silicone oil and an optical waveguide made of an epoxy resin are sequentially formed. The peelability promoting film promotes the peelability between the transparent substrate and the optical waveguide with sufficient adhesion that it is not peeled off from the transparent substrate during formation of the optical waveguide. Subsequently, after adhering a multilayer wiring board to the optical waveguide via an adhering layer made of a photosetting resin, the adhering layer is irradiated with light so as to be set, thereby fixing the multilayer wiring board to the optical waveguide.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: June 17, 2003
    Assignee: Sony Corporation
    Inventor: Tsuyoshi Ogawa
  • Patent number: 6573967
    Abstract: A liquid crystal display apparatus has a drive substrate and a facing electrode substrate superimposed and joined each other via spacers and seal materials, wherein the drive substrate carries drive devices for driving liquid crystal material, the facing electrode substrate carries facing electrodes facing to the drive devices. Liquid crystal material is injected between the drive substrate and the facing electrode substrate. The seal materials include an outer seal formed along outer periphery of the drive substrate and the facing electrode substrate and inner seals formed inside of the outer seal, and a space between the out side part of an effective picture element area having drive devices and an inside portion of the outer seal facing to the effective picture element area or an inside portion of the inner seal can be formed in approximately uniform.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 3, 2003
    Assignee: Sony Corporation
    Inventors: Hiromi Fukumori, Hirohide Fukumoto, Kouichi Taniguchi, Syuichi Shima