Patents Represented by Attorney, Agent or Law Firm Hong S. Lin
-
Patent number: 6815981Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.Type: GrantFiled: February 6, 2003Date of Patent: November 9, 2004Assignee: Altera CorporationInventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
-
Patent number: 6759870Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: February 20, 2003Date of Patent: July 6, 2004Assignee: Altera CorporationInventors: Richard G. Cliff, Bahram Ahanin, Craig Schilling Lytle, Francis B. Heile, Bruce B. Pedersen, Kerry Veenstra
-
Patent number: 6750675Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.Type: GrantFiled: July 11, 2002Date of Patent: June 15, 2004Assignee: Altera CorporationInventors: Ramanand Venkata, Chong H. Lee, Rakesh Patel
-
Patent number: 6707315Abstract: A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.Type: GrantFiled: October 17, 2002Date of Patent: March 16, 2004Assignee: Altera CorporationInventor: Bruce B. Pedersen
-
Patent number: 6673085Abstract: Methods for making an anastomotic connection between a first conduit and a second conduit in a patient. The first conduit and a second conduit of the patient are placed relatively adjacent to each other at the operative site to make a side-to-side anastomosis connection. A region is created where the first conduit and the second conduit contact each other. An adhesive is placed in the region between the two conduits. An aperture is then created in the region with a cutting instrument. A ring of sutures or other fasteners may be used in place of or in addition to the adhesive. An end-to-side anastomosis may be used instead of a side-to-side anastomosis.Type: GrantFiled: May 18, 2001Date of Patent: January 6, 2004Assignee: St. Jude Medical ATG, Inc.Inventor: Todd A. Berg