Abstract: Recent efforts are underway to develop LSI circuits that operate at power supply voltages of 1-V or lower. It is a desire that this low core voltage circuits interface to 3.3-V I/O supply. A charge pump level converter for dual power supply application is proposed using low power and high speed interface to higher I/O supply. This circuit does not consume DC power it is suitable for low power and high speed interface and can be implemented using complementary metal-oxide-semiconductor (CMOS) fabrication processes.
Type:
Grant
Filed:
February 20, 2003
Date of Patent:
March 8, 2005
Assignee:
Taiwan Semiconductor Manufacturing Company
Abstract: A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.
Type:
Grant
Filed:
October 30, 2002
Date of Patent:
February 15, 2005
Assignee:
Taiwan Semiconductor Manufacturing Company
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