Abstract: Recent efforts are underway to develop LSI circuits that operate at power supply voltages of 1-V or lower. It is a desire that this low core voltage circuits interface to 3.3-V I/O supply. A charge pump level converter for dual power supply application is proposed using low power and high speed interface to higher I/O supply. This circuit does not consume DC power it is suitable for low power and high speed interface and can be implemented using complementary metal-oxide-semiconductor (CMOS) fabrication processes.

Abstract: A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.

Abstract: A method and system is disclosed for enhancing a memorization process by using a mnemonic display implemented with a grid learning system. First, the grid learning system is implemented on a predetermined display area of a display device with a plurality of aligned border sections to form the mnemonic display, the border sections containing one or more guiding elements in a predetermined order. When one or more learning entities to be memorized by a user of the mnemonic display are identified, the learning entities are placed in the grid learning system, wherein the first guiding element contained in each learning entity is aligned with a same guiding element in at least one border section, and wherein the locations of the learning entities with reference to the corresponding border sections assist the user to memorize the learning entities.