Abstract: A method for removing contaminants from a substrate surface having a pattern formed on the surface. The method involves rinsing the substrate and pattern with water to remove acid reactive material. The substrate and pattern are then washed with an acid whose concentration is too low to attack the material that forms the pattern. Then the substrate is washed with water to remove the acid.

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: A method and structure for an integrated circuit technology segment test structure including a plurality of technology test structures connected together as a chain of elements and a plurality of externally probable regions positioned along said chain of elements, said externally probable regions being positioned so as to enable location of a failed test structure.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable. The magnetic device can be programmed into one of three magnetic field orentations or states. Conventional VLSI fabrication steps are used for compatability with low-k dielectric Back-End-Of-Line (BEOL) processing.

Abstract: A method and rotational mask scanning apparatus for exposing a plurality of images on a workpiece, include a rotatable mask having a pattern of image segments thereon, an optical system for projecting the image segments onto the workpiece, and a device for at least one of rotating the mask and for moving the workpiece so as to continuously expose a plurality of regions on the workpiece with the pattern of image segments.

Abstract: A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.

Abstract: A structure and method for polishing a device include oscillating a carrier over an abrasive surface (the carrier bringing a polished surface of the device into contact with the abrasive surface, the oscillating allowing a portion of the polished surface to periodically oscillate off the abrasive surface), optically determining a reflective measure of a plurality of locations of the polished surface as the portion of the device oscillates off the abrasive surface and calculating depths of the locations of the polished surface based of the reflective measure.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: A process for forming capacitors in a semiconductor device.

Abstract: A capacitor structure formed on a semiconductor substrate may include a first interconnect wiring (such as copper damascene) and a first conductive barrier layer in contact with the first interconnect wiring. A first capacitor plate, a capacitor dielectric structure and a second capacitor plate may also be included over the first conductive barrier layer. A second conductive barrier layer may be formed on the second capacitor plate and a second planar insulating structure may be formed over the second capacitor plate. Finally, a second interconnect wiring may be embedded within a second planar insulator structure.

Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.

Abstract: A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

Abstract: A process and apparatus for depositing thin films onto a substrate. The process comprises mounting a wafer onto a wafer chuck and pumping a cryogenic fluid through the chuck which cools the wafer chuck and the wafer to a temperature below about +20° C. A thin film is then deposited over the cooled wafer using a sputter deposition process while maintaining the temperature of the wafer chuck and the wafer below about +20° C. The preferred embodiment of the present invention includes the use of liquid nitrogen as the cryogenic fluid, and copper as the material to be deposited through the sputtering process. In addition, the preferred embodiment cools the wafer chuck and the wafer to a temperature of about −100° C. The apparatus includes the physical vapor deposition vessel, the wafer chuck, the source of material to be deposited, the wafer, and the cooling line which passes through the wafer chuck to carry the cooling fluid to the chuck.

Abstract: A micromechanical sensor probe for a scanned-probe tool includes a silicon cantilever and a silicon tip physically attached to the cantilever. The micromechanical sensor probe has a coating of a refractory metal silicide formed at least on the tip. Titanium silicide is preferred. The probe also has a layer of refractory metal nitride formed entirely over the refractory metal silicide.