Abstract: A method and apparatus for generating a timing signal for a semiconductor device, wherein the timing of rising and falling edges in the timing signal can be very precisely controlled. In one embodiment, a serial data stream derived from data stored in a memory device is applied to the inputs of first and second programmable delay elements each adapted to introduce a delay into the serial data stream. The resulting first delayed serial data stream is applied to the SET input of a flip-flop circuit; the resulting second delayed serial data stream is applied to the RESET input of the flip-flop. The output of the flip-flop constitutes the generated timing signal. The rising and falling edges of the timing signal are controlled through manipulation of the lengths of the delays introduced by the first and second delay elements into the serial data stream. Manipulation of the delay times is accomplished through adjustment of analog programming voltages applied to the respective delay elements.