Abstract: An embedded LSI includes a FeRAM macro block and an associated logic circuit section. A hydrogen barrier layer covers the FeRAM macro block as a whole and exposes the logic circuit section. The edge of the hydrogen barrier layer overlies the peripheral circuit of the FeRAM macro block and the boundary separating the FeRAM macro block from the logic circuit section. The ferroelectric capacitor is protected by the hydrogen barrier layer against hydrogen during a hydrogen-annealing process.

Abstract: In a method for placing an electrode for signal observation, after tracking equipotential wires, conducting the collation to give the correspondence in connection relation and adding the wire name to the collated wire, it is checked out whether the top-layer wire exists about all equipotential wires, if the equipotential wire connected to the top-layer wire exists, the concerned wire name and top-layer wire information are extracted and output. If the equipotential wire connected to the top-layer wire does not exist, it is judged whether the lead-out to the top layer of equipotential wire is possible or not in cases of moving the wire and not moving the wire, then, according to the result, a given processing is conducted. Thus, the placement position of electrode on chip to equipotential wire desired to conduct the signal observation is searched automatically.

Abstract: A differential amplifier circuit includes a first transistor and a second transistor cooperatively forming a current mirror circuit, a third transistor connected in series to the first transistor and connected to an inverted input terminal through which a comparison voltage which is a predetermined constant voltage is input to the third transistor, a fourth transistor connected in series to the second transistor and connected to a non-inverted input terminal through which a feedback voltage which increases in proportion to an output voltage of the third transistor is input to the fourth transistor, a constant current source for supplying predetermined current to the first to fourth transistors, and an offset circuit connected in series to the third transistor, and has a predetermined input offset voltage provided between the inverted input terminal and the non-inverted input terminal.

Abstract: Storing data in a cache memory includes providing a first mechanism for allowing exclusive access to a first portion of the cache memory and providing a second mechanism for allowing exclusive access to a second portion of the cache memory, where exclusive access to the first portion is independent of exclusive access to the second portion. The first and second mechanisms may be software locks. Allowing exclusive access may also include providing a first data structure in the first portion of the cache memory and providing a second data structure in the second portion of the cache memory, where accessing the first portion includes accessing the first data structure and accessing the second portion includes accessing the second data structure. The data structures may doubly linked ring lists of blocks of data and the blocks may correspond to a track on a disk drive. The technique described herein may be generalized to any number of portions.

Abstract: A semiconductor chip is mounted on a bottom plate, on which a side wall surrounding the semiconductor chip is formed. At a position where a lead passes through the side wall, an inner surface of the side wall and that of a ceramic piece lie on the same plane vertical to the bottom plate. Clearances with triangular cross-sections are provided for each boundary surface between the side wall and the ceramic piece so that the ceramic piece is prevented from being cracked by thermal stress. An airtight property of the ceramic package is not deteriorated by the aforementioned clearance.

Abstract: In a digital/analog converter for (m+n)-bit, digital input data, a sigma-delta type pulse modulation circuit receives lower-order n bits of the digital input data to generate 1-bit data corresponding to the lower-order n bits in synchronization with a clock signal. An m-bit adder adds the 1-bit data to upper-order m bits of the digital input data. An m-bit digital/analog conversion section performs a digital-to-analog conversion upon an output value of the m-bit adder. A low-pass filter removes a high frequency component of an output value of the m-bit digital/analog conversion section to generate an analog data corresponding to the (m+n)-bit digital input data.

Abstract: A pair of lightly doped drain (LDD) regions are provided in a thin film transistor of each pixel of a thin film transistor substrate for a liquid crystal display device and a light shielding portion of a material having reflectivity lower than that of a metal and covering a portion or a whole portion of the LDD regions is provided so as to restrict an internal random reflection of light.

Abstract: A resin structure includes a resin layer and a metal layer. The resin layer is formed of a single material. The metal layer is laminated directly on the resin layer without intervention of an adhesive layer between the resin layer and the metal layer. A surface of the resin layer, on which the metal layer is laminated, has a surface roughness of a value in a range of 0.1 microns to 10 microns, as a rough surface. The metal layer is formed on the rough surface of the resin layer.

Abstract: In a display panel manufacturing method and a display device manufactured by the method, a plate-shaped partition wall-forming member is sandwiched between a mold having an inverted shape to partition walls and a support mold to press-mold the partition wall-forming member therebetween, thereby forming a partition wall member comprising partition wall portions and a bottom insulating layer portion while coming into close contact with the mold. Thereafter, the partition wall member is transferred onto a display substrate to complete a display panel.

Abstract: First, a mask pattern is defined to a plurality of lattice shaped regions of a uniform dimension. Then, the lattice shaped regions which are adjacent to each other are assigned to different complementary masks. In this manner, the shape of an opening through which electron beams pass is determined so that a displacement caused by a stress acting to each location in the complementary masks is less than a predetermined value.

Abstract: An EEPROM is incorporated in a single chip microcomputer for storing programmed instruction codes, and is tested before separation of a semiconductor wafer into semiconductor chips, wherein pads used in the EEPROM test are arranged along an edge of the semiconductor chip so as to permit an external tester to concurrently bring two rows of probes into contact therewith, thereby improving the testability.

Abstract: A lower aluminum line is exposed to a via-hole formed in an inter-level insulating layer, and an outgassing is carried out before deposition for an upper aluminum line connected through the via-hole to the lower aluminum line, wherein the outgassing is carried out at a substrate temperature equal to or less than the maximum substrate temperature in the formation of the inter-level insulating layer so that a hillock and a whisker due to the thermal stress do not take place in the lower aluminum line.

Abstract: A shelf system has supporting rods (2) and shelf boards (3) provided with fastening devices for fastening them to the supporting rods (2) at various heights. The supporting rods are usually arranged in the comer areas of the rectangular shelf boards. Bores are pierced at certain heights in the supporting rods into which fastening elements such as supporting pegs can be plugged to hold the shelf boards at the corresponding height. The object of the invention is a novel shelf system which allows the height of the shelf boards to be continuously adjusted and in which the position of the shelf boards can be adjusted within a certain angular range.

Abstract: There is provided a semiconductor device including (a) a substrate, (b) a semiconductor chip mounted on the substrate, (c) a wall having a closed cross-section and mounted on the substrate such that the semiconductor chip is surrounded by the wall, and (d) a cover covering the wall therewith so that a closed cavity is defined by the substrate, the wall and the cover, the cavity being designed to be under a pressure almost equal to an atmospheric pressure at a temperature highest in both steps of fabricating the semiconductor device and steps expectable after the semiconductor device is completed. The semiconductor device can prevent defectiveness such as electric leakage and electromigration, and further prevent occurrence of “popcorn” phenomenon which might occur in an annealing step.

Abstract: Semiconductor integrated circuit includes a MPU and a cache memory implemented by a plurality of DRAM macro blocks each disposed between the MPU and bonding pads of the chip. Each DRAM macro block has a redundancy function for replacing a defective row with a redundancy row of memory cells. A plurality of fuse blocks each for storing the row address of the defective row are arranged in a row, with the elongate sides of each of the fuse blocks extending parallel to the signal lines extending between the MPU and the bonding pads. The arrangement allows a large number of signal lines to pass the space between the fuse blocks, thereby allowing a smaller chip size.

Abstract: A non-volatile semiconductor device stores multi-value information of at least two bits in one memory cell. A source region and a drain region serve as diffusion regions. A first channel region and a second channel region are placed between the source region and the drain region. A first gate electrode is arranged over the first channel region and the drain region. A second gate electrode is arranged over the second channel region and the source region. The first channel region stores a first threshold value while the second channel region stores a second threshold value different from the first threshold value.

Abstract: A semiconductor device comprising bolometers arranged in two-dimensional form corresponding to pixels for converting incoming infrared rays into electrical signals includes vertical switches, a vertical shift register, horizontal switches, and a horizontal shift register as means for selecting an arbitrary pixel. The semiconductor device is configured to allow an overcurrent to be supplied to a bolometer in a pixel selected by those means.

Abstract: To provide a non-volatile semiconductor memory device in which the word line resistance can be decreased in resistance without being accompanied by increase in chip area, and a manufacturing method for the non-volatile semi conductor memory device. In a non-volatile semiconductor memory device having a floating gate (203 of FIG. 2) and a control gate (205 of FIG. 2), a contact groove (407 of FIG. 4a) extending in the direction of a word line (102 of FIG. 1) is provided on an interlayer insulating film (404 of FIG. 4a) formed as an upper layer of the control gate, and an electrically conductive member of, for example, tungsten, is embedded in the contact groove to establish electrical connection between the wiring metal (409 of FIG. 4d) formed as an upper layer of the interlayer insulating film and the control gate with a large contact area.

Abstract: A resin-molding mold unit and a resin-molding apparatus having the resin-molding mold unit are capable of removing any air trap from a molten resin therein. This makes it possible to produce a molded product which is free from any void and therefore improved in appearance. In order to enhance demolding of the molded product from the resin-molding mold unit, this resin-molding mold unit has a pin hole in which an ejection pin is received to have its front end portion extend into a molding space from an inner wall surface thereof by a length which is adjustable, if necessary. The front end portion assumes a semispheric shape. In injecting the molten resin, the ejection pin is adjusted in position so as to have its outer peripheral edge portion aligned in level with the inner wall surface. Since the molten resin thus injected flows along the semispheric front end portion, any air trap is not formed in the vicinity of the ejection pin, particularly, in a downstream side thereof.

Abstract: There is provided a semiconductor device including a semiconductor pellet having a plurality of bump electrodes on a surface thereof, a wiring board having a plurality of pad electrodes on a surface thereof, each one of the pad electrodes being engaged to an associated one of the bump electrodes when the wiring board is coupled to the semiconductor pellet, and a resin layer sandwiched between the semiconductor pellet and the wiring board for connecting them with each other therethrough, each of the bump electrodes being formed with one of a projection and a recess into which the projection is able to be fit, and each of the pad electrodes being formed with the other. For instance, the bump electrodes are formed by compressing a molten ball formed at a tip end of a gold wire onto the semiconductor pellet, and the projection is formed on the bump electrodes by cutting the gold wire so that a tip end portion of the gold wire leaves on the bump electrodes.