Abstract: A shadow RAM cell and a non-volatile memory employing a ferroelectric capacitor, and a control method therefor can reduce number of transistors forming a memory cell to permit increasing of capacity comparable with SRAM. The a memory cell includes a flip-flop having a pair of storage nodes, a pair of switching elements controlled ON and OFF by a common word line and controlling connection between a pair of storage nodes and a pair of bit lines, and a pair of ferroelectric capacitors directly connected to the pair of storage nodes at respective one ends and connected to a plate line at the other end.