Abstract: A capacitor in parallel with a CMOS memory is used, in the event of a power outage, to apply a sufficient temporary voltage to the memory to maintain the stored data. Data storage retention time is maximized by a resistor, connected between the capacitor and the memory, having a resistance R approximately given byR = 0.4 (V.sub.i - V.sub.f)/I.sub.f (1)where V.sub.i is the initial voltage on the capacitor, V.sub.f is the minimum voltage for maintaining the data and I.sub.f is the capacitor discharge current at voltage V.sub.f.

Abstract: A low power detector circuit consists of the basic four MOS transistors of an MOS flip-flop and includes another pair of MOS transistors as well as voltage equalization circuitry. The added pair of transistors and the cross coupling of the gates of two of the other transistors results in a detector circuit which automatically limits power dissipation at least by the time the proper output signal levels are attained.

Abstract: A relatively high sensitivity and high speed current detector consists of essentially a common base differential amplifier consistng of two junction transistors, each having separate emitter and collector resistors, and a constant current source connected to the collector resistors. Separate input terminals connected to the emitters allow complementary information current signals or an information current signal and a reference current signal to be applied to the emitter terminals. The output signal and the complement thereof appear at their respective collectors.

Abstract: A 1,024 bit semiconductor memory system, fabricated on a single integrated circuit chip, utilizes dynamic memory cells and low power dynamic control circuitry. An initial input control signal activates the control circuitry which internally generates all the control signals. The timing of all the internally generated control signals is automatically maintained by the control circuits.

Abstract: An improved TTL to MOS voltage level shifter circuit utilizes a totem pole output stage consisting of a pull-up junction transistor and a pull-down saturation junction transistor, an intermediate stage consisting essentially of a saturation junction transistor, an input stage consisting essentially of a diode and a saturation junction transistor, and current spike inhibit circuitry which consists essentially of a saturation junction transistor connected between the input stage and the base of the pull-down transistor. The current spike inhibit transistor, which turns on with the pull-down transistor, has a greater turnoff time than the pull-down transistor and consequently provides a relativley low impedance discharge path connected to the base of the pull-down transistor which allows the pull-down transistor to turn off before the pull-up transistor turns on. This helps insure against output current spikes that occur if the pull-up and pull-down transistors conduct simultaneously.