Patents Represented by Attorney Ido Tuchman
  • Patent number: 8137107
    Abstract: A method, system, and computer program for interacting with team members of a virtual team. Persistent storage is configured to store collective qualifications of the virtual team based on the individual qualifications of the team members, while a team broker is configured to present the collective qualifications to third parties. Thus, the broker provides a dynamic representation of the collective knowledge, skills and experience of a virtual team. The broker further enables an entity, such as a team employer or teacher, to interact with the virtual team as if that team were a single entity, rather than a collection of individual members.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: David F. Bantz, Jarir K. Chaar, Clifford A. Pickover
  • Patent number: 8141059
    Abstract: A method/system for avoiding software conflicts, with library being divided into layer 1 to layer M and M?1.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yong Ding, Xiao Bing Guo, Hui Su, Zhepeng Wang, Shiwan Zhao
  • Patent number: 8138056
    Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
  • Patent number: 8140841
    Abstract: A technique for updating configurations of a target system in a computer. The method comprises booting, based on Preboot Execution Environment technology, a micro-system for updating configurations of a target system before booting the target system, the micro-system performing the steps of: (a) acquiring target configuration packages via a network from a server; (b) extracting target configuration data from said target configuration packages; and (c) updating the configurations of said target system by using said target configuration data, wherein said micro-system is independent of said target system.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Rui Xin Cao, Le He, Xing Jin, Pei Ni Liu, Qing Bo Wang, Ying Zhou
  • Patent number: 8127078
    Abstract: A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache line, and a second cache array coupled to an alignment unit is configured to output a second cache entry associated with the alignment cache line. The alignment unit coupled to the address decoder selects either the target cache line or a neighbor cache line proximate the target cache line as an alignment cache line output. Selection of either the target cache line or a neighbor cache line is based on an alignment bit in the memory address. A tag array cache is split into even and odd cache lines tags, and provides one or two tags for every cache access.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 8120937
    Abstract: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brian L. Ji, Chung H. Lam, Robert K. Montoye, Bipin Rajendran
  • Patent number: 8117456
    Abstract: A method, apparatus and system to ensure the security in the information exchange and to provide list matching with higher efficiency and practicality. In a particular embodiment, each of lists to be subject to list matching is represented as a polynomial having roots equivalent to the items of the list. Then, polynomials generated for the lists to be subject to list matching are added according to a distributed secret computation. A list containing an item equivalent to a root of a polynomial resulting from the addition is created and output as the list of a common item.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Masayuki Numao, Yuji Watanabe
  • Patent number: 8108714
    Abstract: A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Jude A. Rivers, Victor Zyuban
  • Patent number: 8101456
    Abstract: A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott, Yu Zhu
  • Patent number: 8065503
    Abstract: Methods, systems and computer programs for distributing a computing operation among a plurality of processes and for gathering results of the computing operation from the plurality of processes are described.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: November 22, 2011
    Assignee: International Business Machines Corporation
    Inventor: Bin Jia
  • Patent number: 8060941
    Abstract: A method and system for verifying authenticity of an application in a computing-platform operating in a Trusted Computing Group (TCG) domain is provided. The method includes computing one or more integrity measurements corresponding to one or more of the application, a plurality of precedent-applications, and an output file. The output file includes an output of the application, the application is executing on the computing-platform. Each precedent-application is executed before the application. The method further includes comparing one or more integrity measurements with re-computed integrity measurements. The re-computed integrity measurements are determined corresponding to one or more of the application, the plurality of precedent-applications, and the computing-platform.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: November 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bernhard Jansen, Luke J. O'Connor, Jonathan A. Poritz, Elsie A. Van Herreweghen
  • Patent number: 8055589
    Abstract: A system for enabling verification in traceability of a supply chain while maintaining confidentiality of private suppliers. A group signature is applied to an undisclosed supplier. The undisclosed supplier previously receives registration to the certificate authority device, and performs a group signature based on the certificate issued by the certificate authority device. A disclosed supplier and the undisclosed supplier sign and generate a signature chain when they ship parts. A verifier device receives a signature chain with products shipped from the supplier manager device, divides a signature of the disclosed supplier from a signature chain, and verifies the undisclosed supplier from the group signature. Identification of the undisclosed supplier is performed by a third-party auditor system requested to do so by the verifier device by using a group private key.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mika Saito, Yuji Watanabe, Madoka Yuriyama, Takeo Yoshizawa
  • Patent number: 8051010
    Abstract: A method, system and computer program product relating to automatically validating a transaction between an issuer having a signing key, an emitter having an emitter key, an acceptor having a unique identity and a limit on transactions and a validator.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: November 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jan L. Camenisch, Susan R. Hohenberger
  • Patent number: 8042091
    Abstract: Techniques for composition of model transformations from a predetermined set of model transformations. A state machine is provided in memory. The states are defined in the state machine in terms of predetermined model attributes. In response to specification of a target state for an input model to be transformed, an execution sequence in the state machine, between a start state corresponding to the input model and an end state corresponding to the specified target state, is selected. Each transformation in the selected sequence is then successively executed on the input model. After executing each transformation in the selected sequence, the transformed input model state is compared to the model state defined in the state machine to determine if the selected sequence is inoperable for the input model. If so, an alternative execution sequence in the state machine, between the input model state and the specified target state, is selected.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jana Koehler, Jochen M. Kuester, Ksenia Ryndina, Jussi H. Vanhatalo, Michael S. Wahler, Olaf W. Zimmermann
  • Patent number: 8035861
    Abstract: An image of a sample print printed to obtain parameters is picked up by using “a parameter obtaining device” that meets the standards of an instrument for the invention of “the electronic scrap system.” Then, the picked-up image is captured by a DTP system, and color data of a needed position are imported to a parameter DB. Thereby, parameters for simulation to be used in an invisible code printing support system can be easily inputted. Use of this method eliminates the necessity of figuring out parameters through experiments and the like, and of inputting these parameters as numerical values. In addition, since this method uses a physical medium and inks to be actually used, as they are, their optical characteristics, an influence of a blue component of invisible light emitted from an ultraviolet LED, and the like can be inputted all together as a picked-up image.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Noboru Kamijo, Kohichi Kamijoh
  • Patent number: 8030649
    Abstract: Various techniques for testing multicore processors in an integrated circuit. Each core includes a plurality of registers configured to form at least two scan chains. In one embodiment, a verification unit located in the integrated circuit is electrically coupled to outputs of the scan chains. The verification unit is configured to determine the validity of the outputs of the scan chains and to indicate a malfunction of the integrated circuit if the outputs are determined not to be valid.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventor: Michael K. Gschwind
  • Patent number: 8024160
    Abstract: A procurement system may include a dual solution computation unit that creates a qualification problem limited to a delivery schedule and computes a dual solution for a qualification problem. The system includes a schedule search unit that creates a function that constrains a dual solution of constraint equations for a linear relaxation problem of the delivery schedules and searches for a delivery schedule exhibiting constraints that violate the dual solution of the qualification problem. The system further includes a schedule adding unit that creates a new qualification problem by adding and setting a delivery schedule and computes a dual solution to a new qualification problem using the dual solution computation. The system further includes an integer solution computation unit that outputs the number of delivery means and the amount of commodity to be purchased.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventor: Masami Amano
  • Patent number: 8017433
    Abstract: Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Stephen M. Rossnagel, Alejandro G. Schrott
  • Patent number: 7982249
    Abstract: A magnetic tunnel junction transistor. In a particular embodiment, the magnetic tunnel junction transistor includes a tunnel barrier having a high resistance when in a non-ferromagnetic, state and a low resistance when in a ferromagnetic state. The tunnel barrier is switchable between the non-ferromagnetic and the ferromagnetic states.
    Type: Grant
    Filed: June 26, 2010
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7979712
    Abstract: A method, apparatus and system to ensure the security in the information exchange and to provide list matching with higher efficiency and practicality. In a particular embodiment, each of lists to be subject to list matching is represented as a polynomial having roots equivalent to the items of the list. Then, polynomials generated for the lists to be subject to list matching are added according to a distributed secret computation. A list containing an item equivalent to a root of a polynomial resulting from the addition is created and output as the list of a common item.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Masayuki Numao, Yuji Watanabe