Patents Represented by Attorney Infineon Techn. AG Patent Department
  • Patent number: 8351464
    Abstract: In one implementation, a transmission apparatus includes a protocol stack for a DSL transmission system, the protocol stack includes a retransmission functionality, the retransmission functionality being provided between a sublayer of a TPS-TC layer and a data link layer, the retransmission functionality having a fragment of a packet or a group of fragments of a packet as basic retransmission unit. The protocol stack may implement a service specific retransmission functionality such that for a first class of services retransmission protection is provided and for a second class of services no retransmission protection is implemented.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: January 8, 2013
    Assignee: Infineon Technologies AG
    Inventors: Bernd Heise, Michael Horvat, Gert Schedelbeck, Dietmar Schoppmeier
  • Patent number: 8331166
    Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Techn. AG
    Inventors: Cyrille Dray, Alexandre Ney
  • Patent number: 8315024
    Abstract: Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: November 20, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Wolfgang Soldner, Gernot Langguth, David Alvarez, Krysztof Domanski