Patents Represented by Attorney Infineon Technologies
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Patent number: 8243555Abstract: Implementations are presented herein that include a time delay path.Type: GrantFiled: August 7, 2008Date of Patent: August 14, 2012Assignee: Infineon Technologies AGInventors: Stephan Henzler, Siegmar Koeppe
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Patent number: 8242579Abstract: One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.Type: GrantFiled: May 25, 2009Date of Patent: August 14, 2012Assignee: Infineon Technologies AGInventor: Philipp Riess
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Patent number: 8189693Abstract: The invention relates to a digital signal transfer method and apparatus in which a signals are transferred between first and second electrically isolated circuits. An announcement signal is transferred from the first circuit to the second circuit and a data signal is transferred from the first circuit to the second circuit within a data signal time window associated with the announcement signal.Type: GrantFiled: September 30, 2009Date of Patent: May 29, 2012Assignee: Infineon Technologies AGInventor: Bernhard Strzalkowski
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Patent number: 8174426Abstract: A method and a system for converting time intervals are provided. In one embodiment, the system comprises a first time-to-digital converter having a first resolution configured to convert a first time interval, a second time-to-digital converter having a second resolution configured to convert a second time interval, and a third time-to-digital converter having a third resolution and coupled to the first time-to-digital converter and the second time-to-digital converter, the third time-to-digital converter configured to convert a third time interval and a fourth time interval.Type: GrantFiled: September 22, 2010Date of Patent: May 8, 2012Assignee: Infineon Technologies AGInventor: Stephan Henzler
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Patent number: 8143694Abstract: Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.Type: GrantFiled: June 2, 2008Date of Patent: March 27, 2012Assignee: Infineon Technologies AGInventors: Vianney Choserot, Gunther Lehmann, Franz Ungar
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Patent number: 8125202Abstract: The present invention relates to a protection circuit for protecting a half-bridge circuit. The protection circuit detects an incorrect response of the half-bridge by monitoring the current of a first switch at a series resistor of a second switch. The protection circuit has a detector for detecting the voltage across the resistor and an evaluation circuit which is designed in such a manner that it evaluates an output signal from the detector after the first switch has been switched on and provides a fault signal at an output when the voltage across the resistor is greater than the threshold voltage.Type: GrantFiled: August 21, 2008Date of Patent: February 28, 2012Inventors: Martin Feldtkeller, Dieter Zipprick
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Patent number: 8125821Abstract: One or more embodiments are related to a method of operating a phase-change memory array, including: providing the phase-change memory array, the phase-change memory array including a phase-change memory element in series with an access device between a first address line and a power line; causing a first current through the memory element from the first address line to the power line; and causing a second current through the memory element from the power line to the first address line.Type: GrantFiled: June 1, 2007Date of Patent: February 28, 2012Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Thomas Nirschl, Christian Peters, Michael Bollu, Wolf Allers, Michael Sommer
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Patent number: 8101492Abstract: One or more embodiments relate to a method of forming a semiconductor device, including: providing a substrate; forming a gate stack over the substrate, the gate stack including a control gate over a charge storage layer; forming a conductive layer over the gate stack; etching the conductive layer to remove a portion of the conductive layer; and forming a select gate, the forming the select gate comprising etching a remaining portion of the conductive layer.Type: GrantFiled: September 23, 2009Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: John Power, Danny Pak-Chum Shum
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Patent number: 8101477Abstract: One or more embodiments relate to a method for forming a memory device, the memory device including a control gate, a charge storage structure and a select gate, the method comprising: forming a gate tower, the gate tower including the control gate over the charge storage structure; forming a dummy tower laterally spaced apart from the gate tower; and forming a select gate between the gate tower and the dummy tower.Type: GrantFiled: September 28, 2010Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventor: John Power
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Patent number: 8101517Abstract: One or more embodiments may relate to a method for making a semiconductor structure, the method including: forming an opening at least partially through a workpiece; and forming an enclosed cavity within the opening, the forming the cavity comprising forming a paste within the opening.Type: GrantFiled: September 29, 2009Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: Manfred Frank, Ivan Nikitin, Thomas Kunstmann
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Patent number: 8093689Abstract: A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.Type: GrantFiled: July 2, 2007Date of Patent: January 10, 2012Assignee: Infineon Technologies AGInventors: Wolfgang Stadler, Harald Gossner, Reinhold Gaertner
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Patent number: 8081003Abstract: Implementations are presented herein that include a test circuit and a reference circuit.Type: GrantFiled: February 2, 2009Date of Patent: December 20, 2011Assignee: Infineon Technologies AGInventors: Christian Pacha, Thomas Baumann, Georg Georgakos, Anselme Urlick Tchegho Kamgaing
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Patent number: 8072061Abstract: Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region.Type: GrantFiled: March 10, 2010Date of Patent: December 6, 2011Assignee: Infineon Technologies AGInventors: Harald Gossner, Christian Russ, Thomas Schulz, Jens Schneider
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Patent number: 8048734Abstract: One or more embodiments of the invention relate to a method of making a heterojunction bipolar transistor, including: forming a collector layer; forming a stack of at least a second dielectric layer overlying a first dielectric layer, the stack formed over the collector layer; removing a portion of each of the dielectric layers to form an opening through the stack; and forming a base layer within the opening.Type: GrantFiled: October 5, 2009Date of Patent: November 1, 2011Assignee: Infineon Technologies AGInventor: Detlef Wilhelm
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Patent number: 8049336Abstract: One or more embodiments relate to a semiconductor device, comprising: a Si-containing layer; a barrier layer disposed over the Si-containing layer, the barrier layer comprising a compound including a metallic element; a metallic nucleation_seed layer disposed over the barrier layer, the nucleation_seed layer including the metallic element; and a metallic interconnect layer disposed over the nucleation_seed layer, the interconnect layer comprising at least one element selected from the group consisting of Cu (copper), Au (gold), and Ag (silver).Type: GrantFiled: September 30, 2008Date of Patent: November 1, 2011Assignee: Infineon Technologies, AGInventor: Heinrich Koerner
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Patent number: 8020018Abstract: A circuit arrangement is provided comprising a first partial circuit to receive a supply voltage, a second partial circuit to receive an output signal of the first partial circuit and a first clock signal, the second partial circuit to store the output signal of the first partial circuit depending on the first clock signal, and a control unit to decouple the supply voltage from the first partial circuit for a time period that is shorter than a cycle duration of the first clock signal, wherein the control unit is configured to receive a second clock signal which is derived from the first clock signal by delaying.Type: GrantFiled: September 26, 2007Date of Patent: September 13, 2011Assignee: Infineon Technologies AGInventors: Peter Hober, Knut Just
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Patent number: 7989919Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.Type: GrantFiled: June 3, 2009Date of Patent: August 2, 2011Assignee: Infineon Technologies AGInventors: Josef Boeck, Karl-Heinz Allers, Klaus Goller, Rudolf Lachner, Wolfgang Liebl
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Patent number: 7986023Abstract: One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.Type: GrantFiled: September 17, 2007Date of Patent: July 26, 2011Assignee: Infineon Technologies AGInventors: Helmut Tews, Hans-Gerd Jetten, Hans-Joachim Barth
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Patent number: 7978504Abstract: One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.Type: GrantFiled: June 3, 2008Date of Patent: July 12, 2011Assignee: Infineon Technologies AGInventors: Ronald Kakoschke, Harald Seidl
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Patent number: 7921148Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.Type: GrantFiled: August 9, 2006Date of Patent: April 5, 2011Assignee: Infineon Technologies AGInventor: Thomas Kuenemund