Abstract: The invention relates to a digital signal transfer method and apparatus in which a signals are transferred between first and second electrically isolated circuits. An announcement signal is transferred from the first circuit to the second circuit and a data signal is transferred from the first circuit to the second circuit within a data signal time window associated with the announcement signal.

Abstract: The present invention relates to a protection circuit for protecting a half-bridge circuit. The protection circuit detects an incorrect response of the half-bridge by monitoring the current of a first switch at a series resistor of a second switch. The protection circuit has a detector for detecting the voltage across the resistor and an evaluation circuit which is designed in such a manner that it evaluates an output signal from the detector after the first switch has been switched on and provides a fault signal at an output when the voltage across the resistor is greater than the threshold voltage.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the dual fin and single fin transistors.

Abstract: A circuit includes a plurality of first MuGFET devices supported by a substrate and having a first performance level. A plurality of second MuGFET devices is supported by the substrate and have a second performance level. The first and second devices in one embodiment are arranged in separate areas that facilitate different processing of the first and second devices to tailor their performance characteristics. In one embodiment, the circuit is an SRAM having pull down transistors with higher performance.

Abstract: An amplification apparatus includes an amplifier. The amplification apparatus includes a bias voltage circuitry coupled to the amplifier to provide a bias voltage thereto. The amplification apparatus includes a supply voltage circuitry coupled to the amplifier to provide a supply voltage thereto. The supply voltage circuitry is coupled to the bias voltage circuitry. The bias voltage circuitry is configured to provide the bias voltage depending on the supply voltage.