Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.

Abstract: Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be programmed at various points in the manufacturing and distribution cycle, such as but not limited to the memory chip factory, an original equipment manufacturer (OEM), or in the field. In some embodiments, other types of information (e.g., configuration information for the memory device) may also be programmed in this manner.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a conductive layer on a single crystal ferroelectric material, patterning the conductive layer to form contacts, attaching a portion of a circuit on the patterned conductive layer, lapping the single crystal ferroelectric material to a thickness of about 1 to about 10 microns and then etching the single crystal to a thickness below about 25 nm.

Abstract: A microelectronic package comprises a chip stack (110) that includes a substrate (111), a first die (112) over the substrate and a second die (113) over the first die, a first underfill layer (114) between the substrate and the first die, and a second underfill layer (115) between the first die and the second die. The microelectronic package further comprises a fluidic microchannel system (120) in the chip stack, and the fluidic microchannel system comprises a fluid inlet (121) and a fluid outlet (122) connected to each other by a fluidic passage (123).

Abstract: Coefficients for an Minimum Mean Square Error (MMSE) equalizer may be generated without the receiver performing noise power estimation. The noise power may be inferred from knowledge of the Modulation and Coding Scheme (MCS) that is selected by the link adaptation system. The link adaptation system dynamically converges to a data rate, and that data rate implies an Signal-to-Noise Ratio (SNR) range within which the communication device operates. Using the SNR range, an upper end of the range is selected and used as an SNR value for the MMSE equalizer calculations.

Abstract: An embodiment of the present invention provides an apparatus, comprising a transceiver capable of recovering from disjoint clusters in a mesh network by adding an additional Extended Service Set number (ESS Number) information element (IE) in the Beacon and Probe Response frames in at least one access point (AP) in said mesh network and all newly joining APs performing a scan of all channels to detect what channel the extended service set (ESS) is running on its ESS Number and putting this ESS number into their beacons Probe responses.

Abstract: A solder composition includes a reflow-wetting element that is an intermetallic both pre-reflow and post-reflow. The intermetallic releases the reflow-wetting element upon heating. The solder composition includes the intermetallic first phase in a bulk-solder second phase. A method of assembling a microelectronic package includes the intermetallic in a solder. A computing system also includes the intermetallic first phase in the bulk-solder second phase.

Abstract: A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

Abstract: A stacked die package includes a substrate (210, 310), a first die (220, 320) above the substrate, a spacer (230, 330) above the first die, a second die (240, 340) above the spacer, and a mold compound (250, 370) disposed around at least a portion of the first die, the spacer, and the second die. The spacer includes a heat transfer conduit (231, 331, 333, 351, 353) representing a path of lower overall thermal resistance than that offered by the mold compound itself. The heat transfer path created by the heat transfer conduit may result in better thermal performance, higher power dissipation rates, and/or lower operating temperatures for the stacked die package.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.

Abstract: Flow solutions for cooling one or more microelectronic device(s) are generally described. In this regard, according to one example embodiment, a cooling apparatus comprising a heat sink base coupled with a plurality of fins includes a first pathway for a fluid to flow across one or more of the fins and a second pathway for a fluid to flow across one or more fins in a direction substantially opposite the fluid in the first pathway.

Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.

Abstract: An embodiment of the present invention provides an apparatus, comprising a wireless station operable in a wireless local area network, the wireless station capable of automatic discovery of other stations in a basic service set (BSS) which are capable of supporting direct link setup (DLS).

Abstract: A test pin includes a compression element (110), a first tip (120) physically coupled to a first end (111) of the compression element, a second tip (130) physically coupled to a second end (112) of the compression element, a first arm (140) physically coupled to a first side (121) of the first tip, and a second arm (150) physically coupled to a second side (122) of the first tip.

Abstract: A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.

Abstract: In some embodiments, a heatsink includes a thermally conductive core and at least ten thermally conductive fins extending quasi-radially from the thermally conductive core, wherein most of the fins are of uniform length, and wherein at least a portion of the thermally conductive core is shaped such that the fins having uniform length form a substantially rectangular cross sectional form factor. Other embodiments are disclosed and claimed.

Abstract: An embodiment of the present invention provides a method of pre-allocating and communicating IP address information during wireless communication by an access point, comprising pre-caching by said AP a predetermined number of IP addresses from a backend Dynamic Host Configuration Protocol (DHCP) server. An embodiment may further comprise providing by said AP an IP subnet roaming information element that provides the IP Address that a wireless station (STA) will be obtaining if a wireless station (STA) roams to a particular AP and providing by said AP an IP subnet roaming information element that provides an IP subnet mask that determines the network address and host address portion of the IP addresses and providing by said AP provides an IP subnet roaming information element that provides that provides a Default gateway router address.