Patents Represented by Attorney IP Strategy Group PC
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Patent number: 7162630Abstract: An architecture for implementing host-based security such that data security may be applied whenever the confidential data leaves a host computer or a networked device. The improved method and architecture may be implemented in a single integrated circuit for speed, power consumption, and space-utilization reasons. Within the integrated circuit, a combination of hardware-implemented, network processor-implemented, and software-implemented functions may be provided. The innovative host-based security architecture may offer line-rate IPSec acceleration, TCP acceleration, or both.Type: GrantFiled: August 30, 2002Date of Patent: January 9, 2007Assignee: Adaptec, Inc.Inventors: Todd Sperry, Sivakumar Munnangi, Shridhar Mukund
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Patent number: 7046681Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.Type: GrantFiled: August 24, 2001Date of Patent: May 16, 2006Assignee: Raza Microelectronics, Inc.Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
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Patent number: 7028069Abstract: The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.Type: GrantFiled: November 27, 2001Date of Patent: April 11, 2006Assignee: Raza Microelectronics Inc.Inventors: Edward T. Pak, Sivakumar Doraiswamy
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Patent number: 6908846Abstract: A method for controlling a plasma etch process while etching a layer stack having a first layer disposed above an end-point generating layer is disclosed. The method includes etching through the first layer and at least partially through the end-point generating layer while monitoring an absorption rate of a light beam traversing an interior portion of the plasma processing chamber, wherein the end-point generating layer is selected from a material that produces a detectable change in the absorption rate when etched. The end-point generating layer is characterized by at least one of a first characteristic and a second characteristic. The first characteristic is an insufficient thickness to function as an etch stop layer, and the second characteristic is an insufficient selectivity to etchants employed to etch through the first layer to function as the etch stop layer. The method additionally includes generating an end-point signal upon detecting the detectable change.Type: GrantFiled: March 27, 2003Date of Patent: June 21, 2005Assignee: Lam Research CorporationInventors: Brian K. McMillin, Eric Hudson, Jeffrey Marks
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Patent number: 6907478Abstract: A method for facilitating transfer of data between a master block and a slave block through a bus. The method includes ascertaining a transfer size of the data. The method also includes designating a first possible transfer size in a set of possible transfer sizes a chosen transfer size, the set of possible transfer sizes including possible transfer sizes ranging from 20 to 2n, where 2n at least equals to the largest transfer size desired between the master block and the slave block, the first possible transfer size presenting the largest possible transfer size in the set of possible transfer sizes that is less than or equal to the transfer size. The method additionally includes transferring a first data portion of the data from the master block to the slave block, the first data portion having a size that is equal to the chosen transfer size.Type: GrantFiled: February 18, 2003Date of Patent: June 14, 2005Assignee: Adaptec, Inc.Inventors: Zhong-Hua Li, Chakradhara Raj Yadav Aradhyula, Srikanthan Tirumala, Prasad Kuncham
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Patent number: 6896765Abstract: A method for processing a plurality of substrates in a plasma processing chamber of a plasma processing system, each of the substrate being disposed on a chuck and surrounded by an edge ring during the processing. The method includes processing a first substrate of the plurality of substrates in accordance to a given process recipe in the plasma processing chamber. The method further includes adjusting, thereafter, a capacitance value of a capacitance along a capacitive path between a plasma sheath in the plasma processing chamber and the chuck through the edge ring by a given value. The method additionally includes processing a second substrate of the plurality of substrates in accordance to the given process recipe in the plasma processing chamber after the adjusting, wherein the adjusting is performed without requiring a change in the edge ring.Type: GrantFiled: September 18, 2002Date of Patent: May 24, 2005Assignee: Lam Research CorporationInventor: Robert J. Steger
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Patent number: 6895367Abstract: A method for modeling and verifying a set of transactions between a set of master devices and a set of slave devices that are coupled via a bus. The method includes determining a set of dependencies for the set of transactions, executing the set of transactions on the bus, and observing the set of transactions for the dependencies. If the set of transactions does not comprise the dependencies, the method additionally includes logging a status for the set of transactions.Type: GrantFiled: November 19, 2002Date of Patent: May 17, 2005Assignee: Adaptec, Inc.Inventor: Douglas Lee
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Patent number: 6889627Abstract: A symmetrical semiconductor reactor for semiconductor processing, comprising a liner, a process chamber, a valve chamber, a slot valve plate, a liner aperture plate, a rod, and an actuator. The liner has a liner aperture adapted to provide passage for a wafer and to receive the liner aperture plate. The process chamber is coupled to the liner and the valve chamber. The actuator is coupled to the slot valve plate and moves the slot valve plate from the “closed” to the “open” position and vice versa. Since the slot valve plate is coupled to the liner aperture plate by the rod, the actuator is capable of moving the slot valve plate and the liner aperture plate at the same time. However, the precise movements of the liner aperture plate are dependent on the particular rod embodiment.Type: GrantFiled: July 3, 2002Date of Patent: May 10, 2005Assignee: Lam Research CorporationInventor: Fangli Hao
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Patent number: 6863462Abstract: An apparatus including a stiffening structure for stiffening a portion of an axle with a first diameter. The apparatus further includes a set of elements, wherein each of the set of elements includes a semi-circular longitudinal channel of a pre-determined length, and further includes a second diameter that is substantially similar to the first diameter. The apparatus also includes an outer surface comprising a set of expanded structures, wherein each expanded structure of the set of expanded structures further includes a set recesses, wherein each of the elements can be coupled together around the axle with the set of expanded structures, and wherein the amount of deflection of the axle is substantially reduced for the pre-determined length.Type: GrantFiled: June 13, 2003Date of Patent: March 8, 2005Assignee: Snow Family TrustInventor: Robert E. Snow
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Patent number: 6838832Abstract: Methods for improving the stability of RF power delivery to a plasma load are disclosed. The method includes adding an RF resistor and/or a power attenuator at one of many specific locations in the RF power system to lower the impedance derivatives while keeping the matching circuit substantially in tune with the RF transmission line.Type: GrantFiled: September 26, 2002Date of Patent: January 4, 2005Assignee: Lam Research CorporationInventors: Arthur M. Howald, Andras Kuthi, Andrew D. Bailey, III
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Patent number: 6825050Abstract: An automated process control system configured for controlling a plasma processing system having a chamber, the chamber being configured for processing a substrate. The automatic process control system includes a first sensor disposed within the chamber, the first sensor being configured for making a first plurality of measurements pertaining to a first parameter associated with a structure disposed at least partially within the chamber. The performing the first plurality of measurements is performed during the processing of the substrate. The automatic process control system further includes first logic coupled to receive the first plurality of measurements from the first sensor. The first logic is configured for analyzing using SPC methodologies the first plurality of measurements during the processing.Type: GrantFiled: June 7, 2002Date of Patent: November 30, 2004Assignee: Lam Research CorporationInventors: Chung-Ho Huang, John A. Jensen
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Patent number: 6821378Abstract: A cylindrical pump baffle fitted to a semiconductor processing chamber is disclosed. The pump baffle contains a screen with bores therethrough to allow process gasses from the process chamber to be exhausted from the chamber at a reduced rate. This decreases process discrepancies to the wafer due to the prejudice of gas concentration as a result of the pressure differential imposed upon the gas and thereby the wafer brought about by the rapid and relatively unimpeded exit flow of process gasses when no restrictive member is in place. The pump baffle is also machined such that it does not block the placement and removal of wafers by the platform robot arm.Type: GrantFiled: May 25, 2002Date of Patent: November 23, 2004Assignee: Lam Research CorporationInventors: John Daugherty, Neil Benjamin, Song Huang