Abstract: A process for the manufacture of a multilayer ceramic substrate includes fabricating the multilayer ceramic substrate from a monolith fabricated from universal layers and a monolith fabricated from custom layers. The universal layer monolith and the custom layer monolith are then joined to form the complete structure of the MLC substrate.

Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Abstract: A method for determining the memory cell stability of individual memory cells included within a memory array is disclosed. In an exemplary embodiment, the method includes presetting each memory cell to a first logic state and then applying a gradually increasing, controlled leakage current to a node within each memory cell. The voltage of each of the nodes within each corresponding memory cell is then monitored. Then, for each memory cell within the memory array, the level of leakage current which causes the memory cell to be changed from the first logic state to a second logic state is determined. The level of leakage current which causes the memory cell to be changed from the first logic state to the second logic state corresponds to the threshold voltage of a pull-up PFET within the memory cell.

Abstract: A method of adjusting a lithography system or tool to enhance image quality correction is presented. The method enhances image quality correction by using a reduced dose during exposure of the lithographic test patterns. A typical lithography system (tool) comprises an exposure column unit and a control unit. The exposure column unit generates a shaped beam and directs this shaped beam through lenses and a series of deflectors to a mask which is positioned on a movable stage. The control unit provides control management for the components of the exposure column unit. The system maximizes pattern resolution using a mask having test pattern geometries that are at least the same size as the geometries of the pattern of a production mask. The reduced exposure dose used for the lithographic test patterns results in greater sensitivity to small beam setup errors.

Abstract: A positioning stage has a base which carries a stage plate slidably on its upper surface. Three rotatable drives engage both the stage plate and the base to move the stage plate on the base to provide motion along the x and y axes plus rotation. The linear drives each include a motor and a capstan driven by the motor and a drivebar frictionally coupled to the capstan. The stage is spring loaded to provide constant down-load force, regardless of the varying extension length of the drivebar. A ball joint permits varying between the cones and the ball of the ball joint dynamically to desired levels. Pitch, roll, and movement in the Z-axis are precisely maintained by the stage plate. X and Y position are determined by an X interferometer and a Y interferometer, respectively. Yaw is measured by a yaw sensor device for determining yaw angle comprising a light emitting source and a position sensing detector, which generates an analog signal that is the input to a yaw servo to correct yaw error.

Abstract: Described herein is a method for selectively enlarging vias connecting two different layers of conductors in a semiconductor device. Whether or not an individual via is extended on each of its edges is determined by the distance of the edge to the neighboring features. Since many vias can be selectively enlarged along one or more edges without infringing upon neighboring structures, via integrity and conductive characteristics are improved.

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract: A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness rangin

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

Abstract: Disclosed is a method of providing variant fills in a semiconductor substrate having a plurality of trenches by providing a semiconductor substrate with a first set of trenches and a second set of trenches, filling all the trenches with a first fill material, masking the second set of trenches in a manner effective in resisting an etching of said first fill material, etching the first fill material in the first set of trenches to a depth effective in permitting the first set of trenches to be plugged, plugging the first set of trenches with a material resistant to an etching of the first fill material, etching the first fill material from the second set of trenches; and then filling the second set of trenches with a second fill material. The process may be generalized to more than two fill materials.

Abstract: A method and apparatus for processing sheets, includes placing a sheet on a carrier to form a sheet/carrier structure, sizing the sheet/carrier structure, stacking the sheet/carrier structure in a stacking apparatus having a second sheet stacked in advance therein, so that the sheet contacts the second sheet, aligning the sheets with pins, tacking the sheet to the second sheet and removing the carrier.