Abstract: A method and structure for a method of manufacturing a device having different types of transistors, wherein gates of the different types of transistors in the device comprise different materials. The method comprises depositing a silicon layer on a gate dielectric layer, depositing a first-type gate material on the silicon layer, removing the first-type gate material from areas where a second-type gate is to be formed, depositing a second-type gate material on the silicon layer in areas where the first-type gate material was removed, and simultaneously patterning the first-type gate material and the second-type gate material into first-type and second-type gates, and anneal and transform the two types of gate materials.

Abstract: A method of processing greensheets for use as microelectronic substrates comprises providing a greensheet having a width, a length and a thickness, bonding to the greensheet, within the greensheet width and length, a frame adapted to constrain movement of the greensheet within the frame, processing the greensheet and bonded frame, and removing the frame from the processed greensheet. The processing of the greensheet and bonded frame may include punching vias in the greensheet, filling the vias in the greensheet with conductive material, patterning the greensheet by applying conductive paste to the vias and greensheet surface, stacking the patterned greensheet and bonded frame with at least one other patterned greensheet and bonded frame, and laminating the greensheets. The frame is preferably removed from the processed greensheet after laminating the greensheets, and before the laminated greensheets are subsequently sintered.

Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract: A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.

Abstract: A module or assembly is formed by interposing a polymer between a carrier and a semiconductor device to be secured to the carrier. The polymer has ionized metallic particles suspended in it. Before setting or curing the polymer, the module is exposed to an electric field which induces migration of the metallic particles to the opposing pads of the carrier and semiconductor device. Such migration ultimately forms metal dendrites extending between mating pad pairs. The dendrites establish a metallurgical bond and conductive paths between the carrier and the overlying semiconductor device. When the polymer is subsequently set, the carrier and device are not only adhered to each other, but the dendrite connections are fixed and structurally reinforced to provide the needed electrically conductive paths.

Abstract: A detailing tool for processing electronic component substrate includes a supporting frame, a substrate carrier movable on the supporting frame to receive and secure the substrate during processing by the tool, and a pair of cutter assembly attached to said supporting frame for removing tails on said substrate. The cutter assemblies self-align “to” the substrate during initial substrate loading in a processing area of the tool. Each cutter assembly includes a pair of spaced, translatable and opposed cutters that simultaneously move towards each another while removing the tails from the corners of the substrate that remains stationary. The pair of cutter assemblies are symmetrically attached to the supporting frame with respect to an axis for indexing the substrate. Thus, the invention provides a tool for cutting tails from opposite corners on the substrate edge automatically and simultaneously during processing.

Abstract: A method, system and structure for a pin grid or pad grid array structure includes a plurality of pins connected to an electronic structure, a power plane within the electronic structure electrically connected to power pins, a ground plane within the electronic structure, and fuse portions electrically connecting the ground plane to ground pins and signal pins. The power plane and the ground plane create a charge in the pins during electroplating of the pins. The fuse portions disconnecting the signal pins from the ground plane after the electroplating.

Abstract: A fixture and process for assembly of semiconductor modules. Each module comprises a substrate and a cover attached to the substrate. The fixture comprises a baseplate adapted to accept the substrate and a spring-loading device containing a shape memory alloy spring engaging the cover. The shape memory alloy spring exerts a lesser force at room temperature and an elevated force at the bonding temperature of the bonding agent used to attach the cover to the substrate.

Abstract: A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.

Abstract: A method and connecting structure includes a first surface and a connection pad on said first surface, wherein, said first surface includes an opening adjacent to said connection pad, and wherein, upon sufficient stress, said opening forms a flap allowing a portion of said connection pad to separate from said first surface.

Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

Abstract: A chip scale package with outer dimensions for high of semiconductor chips to facilitate handling, testing, and later attachment of the package to further electrical circuitry. The chip scale package has four main components: semiconductor chip, a lead frame, a connection between the semiconductor chip and the lead frame, and an encapsulation sealing the semiconductor chip from the surrounding atmosphere. The semiconductor chip has a body, an active surface, and the dimensions that are between about 70% and 80% of the outer dimensions of the chip scale package. The lead frame has an intermediate path directly in line with, and perpendicular to, the surface of the semiconductor chip, thereby minimizing parasitic inductance and capacitance, and a thermal or ground slug.

Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.

Abstract: A method for minimizing formation of cracks at junctions between conductive vias and conductive lines in line-to-via connections on a substrate. The method comprises providing a transition zone connected between a base section of the line and a cap, the transition zone providing a volume of conductive paste during a conductive paste screen printing operation that is greater than the volume provided by the base section being directly connected to the cap. In particular, the transition zone volume is an effective amount to prevent necking of the conductive line into the via when the mask is misaligned to the substrate within an expected alignment tolerance. The transition zone may comprise a jogged end extending from the base section to the cap at an angle to the line, or a flared end extending from the base section. Line-to-via connection structures, patterns on a mask for making such structures, and masks having such patterns are also disclosed.

Abstract: A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.

Abstract: A method and structure for forming an integrated circuit chip having multiple-thickness gate dielectrics includes forming a gate dielectric layer over a substrate, forming a sacrificial layer over the gate dielectric layer, forming first openings through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor above the first gate dielectric in the first openings, forming a second opening through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor in the second opening.

Abstract: A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer.

Abstract: A method and apparatus for electronic chip assembly maintains a thin gap spacing between the chip and the lid or heat sink and provides for the electronic chip to operate at a relatively cool temperature. The thermal performance is enhanced by a thermal interface material provided in the thin gap and maintained at a minimal thickness as a result of the structure and assembly process. A thin thermal interface material layer may be achieved with a compression step to compress the thermal interface material before the sealant is cured. In addition, a vent hole is provided in the assembly to prevent pressure build-up inside the module during sealant cure. As the sealant is cured, the gap spacing is maintained, further compression of the thermal interface material is not required, and seal defects are prevented.