Patents Represented by Attorney Irving S. Rappaport
  • Patent number: 7797452
    Abstract: The present invention is related to a method and system for facilitating the integration of a plurality of dissimilar systems by allowing networks of integration framework installations and/or other compatible B2B servers to inter-operate across corporate enterprise boundaries to integrate the disparate systems operating within each corporate enterprise.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 14, 2010
    Inventors: Mitchell T. Christensen, Danny R. Sojka
  • Patent number: 7143190
    Abstract: The present invention is related to a method and system for facilitating the integration of a plurality of dissimilar systems by allowing networks of integration framework installations and/or other compatible B2B servers to inter-operate across corporate enterprise boundaries to integrate the disparate systems operating within each corporate enterprise.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: November 28, 2006
    Inventors: Mitchell T. Christensen, Danny R. Sojka
  • Patent number: 5235663
    Abstract: An optical interconnect structure, formed on a substrate, includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. A cladding layer surrounds each core member. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the first predetermined index of refraction. At least one optical port exposes at least a portion of the core member of at least one optical interconnect. The optical port may be located on a top portion of an optical interconnect or at one or both ends of an optical interconnect.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: August 10, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 5208838
    Abstract: A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: May 4, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Dennis L. Wendell, Charles Hochstedler, Dan Lunecki, Terry L. Lyon
  • Patent number: 5208186
    Abstract: In a semiconductor device tape assembly bonding process the fingers of a copper tape are reflow soldered to metal bumps located on the semiconductor device. First, the semiconductor wafer is covered with a conductive film composed of thin layers of aluminum, nickel-vanadium alloy and gold. The bumps are then created by electroplating gold through openings in a photoresist mask. The gold bumps are overcoated with a contolled thickness tin layer and the tin is overcoated with a thin gold anticorrosion layer. The copper assembly tape is coated with a thin gold layer and are lightly pressed against the bumps by means of a thermode. The thermode is quickly heated to a temperature well above the gold-tin eutectic melting temperature and then rapidly cooled. The tin layer on the bump will combine with the adjacent gold to form a liquid phase eutectic which will form and contact both the copper finger and the gold bump. Upon cooling the eutectic melt will solder the finger to the bump.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: May 4, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Ranjan J. Mathew
  • Patent number: 5202645
    Abstract: Operational amplifiers are often used in unity gain configurations where the output is fed back to the input. In the noninverting buffer configuration the output is directly connected to the inverting input and the circuit becomes a voltage follower. In many cases, the input stage includes cascode coupled transistors which isolate the current mirror load from the differentially operated input transistors. Such cascode transistors act to increase gain to reduce noise and to increase the power supply rejection ratio. When cascode coupled transistors are employed the frequency compensation capacitor can be isolated from loading effects on the input stage, thus, further enhancing the value of a cascoded input stage. However, when such an operational amplifier is operated as a unity gain device its transient response can suffer. Negative output transitions can result in circuit ringing following the negative output transient steps.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: April 13, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Christina P. Q. Phan, James B. Wieser
  • Patent number: 5200802
    Abstract: ROM cell programmed ON has N+ source implant spaced a given distance from the gate with LDD bridging the gap between the N+ source and the N channel. ROM cell programmed OFF has P+ implanted into this gap so as to completely override the LDD in this gap. The P+ prevents the N channel from forming ohmic connection to the N+ source.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: April 6, 1993
    Assignee: National Semiconductor Corporation
    Inventor: William E. Miller
  • Patent number: 5198008
    Abstract: An optical interconnect structure, formed on a substrate, optically interconnects optoelectronic transmitting and receiving devices. The optical interconnect structure includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. The ends of the core members are chemically bonded either to an optoelectronic device or a core member of another optical interconnect. A cladding layer surrounds each core member. Each end of a cladding layer proximate to an optoelectronic device is chemically bonded to that device. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the magnitude of the first predetermined index of refraction.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: March 30, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 5197999
    Abstract: A pad for planarization by mechanical polishing of a dielectric layer formed over features on a wafer in the manufacture of semiconductor devices has a substantially planar polishing face. The pad includes a soft matrix material and a substance for stiffening distributed in the pad so as to effect stiffening of the pad. The substance for stiffening is composed of a hard substance, which in a preferred embodiment is in the form of discrete particles distributed substantially uniformly throughout substantially all of the pad.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: March 30, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 5195729
    Abstract: A carrier for a semiconductor wafer or other substrate has an outer portion adapted for engagement by equipment for processing wafers. Interior to the outer portion a substantially planar supporting surface is provided. A retaining lip is provided above the plane in which the supporting surface lies by at least the height of a wafer of a selected size. The circumference of the retaining lip is of sufficient size and proper shape to permit the passage of a wafer of the selected size. The carrier is undercut under the lip, whereby a wafer of the selected size, when placed on the supporting surface, may be retained.In one embodiment, the carrier has a cylindrical shape. The top of the carrier includes a flat outer ring-like surface. The supporting surface and the circumference of the retaining lip are both circular.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: March 23, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Michael E. Thomas, Satoshi Sekigahama, Richard von Salza Brown
  • Patent number: 5192712
    Abstract: A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.
    Type: Grant
    Filed: April 15, 1992
    Date of Patent: March 9, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Amolak Ramde
  • Patent number: 5187389
    Abstract: An integrated circuit which will produce a switched output when the circuit power supply drops a predetermined level below which reliable IC operation is not assured. This reduced power supply condition is referred to as brownout wherein the switching is related to the active devices. A preferred CMOS circuit is disclosed. The switching level is related to the N channel and P channel transistor sum of thresholds which makes the CMOS circuit process adaptive. The circuit is provided with a transistor gate oxide capacitor for improving noise immunity while achieving maximum utilization of IC chip area. In addition, output enable and circuit shutdown capabilities are detailed.
    Type: Grant
    Filed: May 3, 1991
    Date of Patent: February 16, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Christopher M. Hall, Kenneth E. Dubowski
  • Patent number: 5185653
    Abstract: A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing plates which have dimensions that are larger than the bead form the upper and lower surfaces of the package. These plates can be formed of any suitably rigid material. They may be composed of ceramic in low power devices. For high power operation at least one metal plate can be employed. The chip or chips are connected to the lead frame and, along with the top and bottom plates, is located in a transfer mold. The plates are in registy and located so that their outer edges extend beyond the O-ring bead. The mold cavities include faces which press against the plates which are held apart by the O-ring bead so that the bead is compressed by the mold closure.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: February 9, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Andrew P. Switky, Chok J. Chia
  • Patent number: 5180932
    Abstract: A sample and hold circuit is disclosed in which differentially coupled input stages are multiplexed to drive a common output stage. In this way, a plurality of input stages can be employed wherein the transition between sample and hold modes produces greatly reduced switching transients. The circuit has very high overall gain so that sampling accuracy is improved and a very low current input stage configuration permits the use of small hold capacitors without introducing excessive droop in the hold mode. The differential balance is completed by a dummy hold capacitor which is switched along with the hold capacitor. Both of these capacitors are switched in a virtual ground configuration.
    Type: Grant
    Filed: March 11, 1991
    Date of Patent: January 19, 1993
    Inventor: David W. Bengel
  • Patent number: 5181205
    Abstract: A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: January 19, 1993
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Kertis
  • Patent number: 5160859
    Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: November 3, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Dennis L. Wendell
  • Patent number: 5157322
    Abstract: In an integrated circuit a PNP current mirror can lose its current reflection accuracy when low Beta transistors are involved. Since the conventional PNP transistors can often have low Beta this can become a serious problem particularly with high current gain plural output current mirrors. In the invention a compensation current is fed to the current mirror to increase the PNP transistor base currents as an inverse function of Beta. Several alternative circuit embodiments are also disclosed.
    Type: Grant
    Filed: August 13, 1991
    Date of Patent: October 20, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Willam D. Llewellyn
  • Patent number: 5153882
    Abstract: A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.
    Type: Grant
    Filed: March 29, 1990
    Date of Patent: October 6, 1992
    Assignees: National Semiconductor Corporation, Control Data Corporation
    Inventors: Terry L. Lyon, Jeff Chritz
  • Patent number: 5151378
    Abstract: A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.
    Type: Grant
    Filed: March 31, 1992
    Date of Patent: September 29, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Amolak R. Ramde
  • Patent number: 5150019
    Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein a layer of a dielectric medium is disposed between the metal layers. A third metal layer is disposed above the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is disposed above the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: September 22, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Michael E. Thomas, Kranti V. Anand, deceased