Abstract: An apparatus for automatically selecting a processor clock frequency multiplier is disclosed. The apparatus includes a reset circuit that transmits a reset signal to a processor. When the reset signal is deasserted, the processor samples the states of various strapping signals that are provided by the apparatus. The states of the various strapping signals are determined by a clock frequency multiplier indicator circuit in the apparatus. The apparatus also includes a processor failure detection unit that determines if the processor fails to function properly after reset. If the processor failure detection unit determines that the processor is not functioning properly, the clock frequency multiplier indicator circuit indicates a smaller clock frequency multiplier and a new reset of the processor is performed by asserting the reset signal.