Abstract: A cantilevered clip is provided for holding a stack of at least one tray and tray cover. Stack compressive forces applied by the clip are substantially limited to tray and cover edge portions. The clip has a channel base with left and right side walls attached for restricting movement of a stack in left and right directions. Pressure members are positioned orthogonal to at least one wall. An aperture is located adjacent to each pressure member and partially extends into each wall. Protrusions above the base extend inward towards the walls of the channel for captivating the stack in an upward direction.

Abstract: An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.

Abstract: A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data.

Abstract: Comparator chain total offset, static and dynamic, is reduced by injecting a compensation quantity in at least one point in the chain of comparator components. The compensation quantity is determined by providing the comparator chain with calibration signals having equal values and evaluating the output states of the comparator chain. The compensation quantity is adjusted until the probabilities of high and low output states are substantially equal and a calibrated value for the compensation is determined.

Abstract: A wire drawing machine comprises a wire supply unit with an unwinding bobbin for unwinding a wire, a wire drawing unit or units for drawing and reducing the diameter of the wire, and a wire winding unit for winding the drawn wire. Each wire drawing unit comprises: a dancer roller for applying back tension to the wire; a wire drawing die for reducing the diameter of the wire; and a capstan for winding and transporting the wire without slip to apply front tension to the wire. The dancer roller is linearly moved substantially in parallel to direction of wire drawing of the wire drawing die, whereby the wire drawing unit can be reduced in width. A plurality of such wire drawing units can be placed between the wire supply unit and the wire winding unit in multiple rows so as to further reduce the width of the wire drawing machine.

Abstract: A clip is provided for holding a stack of at least one tray and tray cover. Stack compressive forces applied by the clip are substantially limited to tray and cover perimeter rail portions. The clip has a channel base with left and right side retaining walls attached for restricting movement of a stack in left and right directions. Left and right rods protrusions above the base extend inward towards the walls of the channel from the left and right side walls respectively for captivating the stack in an upward direction. Spring protrusions extend upward from the base on input and output ends of the channel, and are configured for applying an upward spring force on opposing bottom edge areas of the stack.

Abstract: The invention concerns a tray having an integral latch that mates to a boss of an adjacent tray to form a stable stack. The latch may be incorporated into any type of tray, basket, or other container for storing articles. Multiple containers may be stacked together without the use of a detachable clip. Also disclosed is a tray that includes an array of posts extending downward to support the tray on a flat surface.

Abstract: A wafer container comprising a base and a cover that nest together. The cover includes tabs on a lower portion that engage notches on the frame. The cover can be combined with the base without indexing to a precise opening on the frame. A handle on the cover enables an operator to easily rotate the container into a locked position. A ribbed pattern on the exterior surface of the frame enables the wafer container to be stacked with another wafer container.

Abstract: An injection molded container for storing and transporting wafers includes a base having a wafer area upon which to place a stack of a plurality of wafer assemblies, wherein each wafer assembly includes a wafer frame upon which is mounted a wafer. A protective wall apparatus is positioned around the wafer area, and includes at least one wall contour artifact. Each wafer frame according to the invention includes a corresponding opposite/mating artifact. The wall apparatus and wafer frame are configured so that the wafer frame must be oriented to mate the wall and frame artifacts in order for the wafer frame to be installed in the container.

Abstract: An injection molded container for storing and transporting wafers includes a base having a wafer area upon which to place a stack of a plurality of wafers. A protective wall surrounds the wafer area, and extends upward, having a first perimeter at the base and a second perimeter at a top wall extremity that is greater than the first perimeter, resulting in the wall being positioned with a draft angle to a line perpendicular to a plane of the base so as to facilitate removal of the container from an injection mold. This invention provides a plurality of wafer positioning columns, each having a surface with a line of contact rising perpendicular to the plane of the base. The lines of contact are positioned so as to restrict movement of a stack of wafers placed in the container.

Abstract: A clip is provided for holding a stack of trays and a tray cover. The clip has a base having a width providing clearance for a width of a tray and a cut-away relief area for finger access. First and second opposing resilient side walls and a resilient back wall extend upward from the base, forming a structure with an open front and top. First and second resilient, elongated and downwardly curved members are included, each having a proximal end attached to an upper front of a corresponding side wall, and a distal end attached to the back wall. The resilient members are positioned so as to apply pressure to first and second opposing perimeter portions of a tray placed in the clip.

Abstract: Apparatus and methods are presented herein for protecting electronic components from damage during transport or “drop testing.” A packaging system of the present invention includes a novel cover tape bonded to a carrier tape, which cover tape includes a foam layer attached thereto on its underside. The foam layer prevents excessive movement of the electronic components within the cavities, thereby protecting the leads and other parts of the components from damage. The method for protecting the components in the cavities of the carrier tape includes attaching the foam layer on the underside of the cover tape before sealing the cover tape on the carrier tape. When the cover tape is bonded to the carrier tape with the components placed in the cavities, the foam layer prevents excessive movement of the components therein.

Abstract: A method for using a moisture-protective container to protect an integrated circuit is disclosed herein. The integrated circuit is placed into a container having a first surface and a second surface that is opposite the first surface, and then the container is closed with a seal. Next, the seal is broken to remove the integrated circuit for evaluation. After evaluation without subjecting the integrated circuit to burn-in, the integrated circuit is restored to the container and the container is resealed with the seal. Lastly, the seal of the container is broken to connect the integrated circuit to a substrate without elevating the temperature surrounding the integrated circuit above the temperature at which evaluation occurred.

Abstract: The present invention concerns a testing object for use in the testing of a wafer clamp. Wafer clamps are used to hold wafers in position on etchers. If the wafer clamp is worn, the process yield drops due to the heating of the wafer and subsequent photoresist melting. The testing object passes wafer clamps having a sufficient wafer overlap distance, but fails wafer clamps without a sufficient wafer overlap distance.

Abstract: A semiconductor integrated circuit suitable for use in an ESD protection circuit is disclosed. A substrate has an active region formed therein so as to define a P/N junction therebetween. An insulating region is formed near the surface of the substrate adjacent the active region thus defining an edge therewith. The active region includes a highly doped portion formed near the surface of the substrate and near the edge of the insulating region and a lightly doped portion formed below the highly doped portion and separated from the edge of the insulating portion. By moving the highly doped portion of the active region away from the insulating region, the P/N junction is effectively moved away from the insulating region.

Abstract: A CMOS Structure is disclosed wherein two adjacent transistors of opposite conductivity each have a gate above their respective channel regions. Spacers are absent from the gate of one of the transistors. The structure is also characterized by lightly doped regions.

Abstract: Semiconductor devices are formed in a semiconductor substrate having an essentially planar upper surface. In some embodiments, implanted regions are formed in the substrate at a first predetermined depth by implantation of oxygen and/or nitrogen ions. In some embodiments buried implanted are formed in the substrate at a second predetermined depth, deeper than the first depth by implantation of oxygen and/or nitrogen ions. These implanted regions are converted to dielectric isolation regions and buried dielectric regions, respectively, by a high temperature anneal after formation of a gate structure.

Abstract: A method for forming trench isolation with spacers on the corners where the silicon and oxide intercept. A cavity is formed in silicon with a mask. Prior to completely removing the mask, the mask is further etched to enlarge the upper portion of the cavity. The cavity is filled with oxide, which is subsequently etched to produce a dome-shaped cap, protective of sharp silicon corners that would otherwise upset electrical characteristics of transistors.

Abstract: A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).