Abstract: A fail-safe multiprocessor system comprises processors connected through a switching unit which forms a data transfer channel between the processors. This switching unit comprises mechanical switches that can selectively connect peripheral units (e.g., display units) with one of the processors. The transfer device constitutes, from the standpoint of each of the connected processors, a normal peripheral unit. The switches are set either manually or automatically under program control by each of the processors. In the case of an error or failure, the data processing system is reconfigured such that the high priority tasks together with their associated peripheral units are transferred from the failed processor to a processor which is still intact.

Abstract: A instruction fetch look-aside buffer with a loop mode control provides for reduced storage contention by storing a program loop in a look-aside buffer during normal mode operations. When the loop is to be executed again loop mode is entered and the instructions are taken directly out of the look-aside buffer without any access of storage required. If the instructions in the look-aside buffer are invalidated during loop mode or if the program loop is exited normal mode operations are resumed.

Abstract: A reconfigurable parallel group of identical functional units and a method for reconfiguring this parallel grouping of identical functional units upon the occurrence of a failure by shifting the contents of the failed unit and the contents of all units between the failed unit and a spare unit one unit toward the spare unit is disclosed. A paired system of input and output busses allows control lines to activate and deactivate the appropriate busses so that a constant input output interface is maintained despite the failure provoked shift. This reconfigurable parallel group can also be stacked together to form larger configurations.