Abstract: A data processing system has a memory bus and a system input/output (I/O) bus including I/O drivers. The memory and I/O buses are controlled by a central processor unit (CPU) for transferring data therebetween and to the I/O drivers. A central clock provides clock signals to the CPU, the memory bus and the I/O bus. The central clock further provides memory and I/O phase alignment signals to the CPU, the alignment signals indicating to the CPU when the start of the CPU clock cycle coincides with the start of a memory bus clock cycle or I/O bus clock signal. Circuit means responsive to the phase alignment and CPU clock signals initiate the transfer of data to the memory and I/O data buses in alternate CPU clock signals to reduce the number of I/O pin switching at any given time thereby reducing the noise and power consumption at the I/O pins and in the system.

Abstract: A multiaddressable highly integrated semiconductor storage is provided, the storage locations of which are addressable by several independent address systems for parallel reading and/or writing. The storage locations are each made up of n storage elements. One storage location consists, for example, of at least two flip-flops which, via coupling elements are connected to associated separate bit and word lines. Each storage location has at least three independently selectable or addressable entry/exit ports permitting the following operations to be executed in parallel: Read word A, read word B, write word C as well as any combination of two or individual ones of those operations. The number of read ports can be increased by providing further address systems and by substituting triple, quadruple, etc., storage cells for a cell pair.

Abstract: Variations of current gain from element to element in a phototransistor array are eliminated by covering the array with an opaque mask and etching openings in the mask over each phototransistor based upon an area reduction factor (ARF). The area reduction factor for an opening is equal to (I.sub.m /I.sub.x).sup.1-n where n is a constant definitive of the change in beta of a phototransistor in the array over a given range of collector currents; I.sub.m is the minimum collector current measured for the array and I.sub.x is the collector current for the phototransistor beneath the opening. Based upon the ARF's, the openings etched in the mask or cover initiate uniform current from each phototransistor element when uniform light flux is directed on the array.

Abstract: Surface leakage paths on bipolar and FET transistors may be significantly reduced by the presence of a fixed charge in an insulating layer adhered to a semiconductor wafer. The fixed charge consists of ions which are introduced into the insulating layer after all high-temperature process treatments have been performed on the wafer. The ions are introduced into the insulating layer by (1) immersing the wafer in a solution of a suitable metal salt; (2) sandwiching the wafers between carefully cleaned non-immersed wafers and (3) driving the ions to the insulating layer-wafer interface by heating the wafer stacks in a furnace at a preselected temperature. The effective charge level embedded in the insulating layer is sufficient to protect against inversion of the wafer surface due to conductors on the insulating layer having negative potentials exceeding 10 volts and overlying the stored-charge area.

Abstract: Logic and analog functions in a complex semiconductor component are stuck fault and parametrically tested through an analog/digital measurement adapter coupled to logic and analog testers. Both logic and analog testers are under computer control whose purpose is to direct the testing sequence, log test results, perform algorithmic calculations on the data and diagnose failing devices in the component under test. The adapter provides the electrical environment to match a range of components under test to the logic and analog testers. The adapter is also under computer control to permit impedance matching of a multiplicity of digitally controlled stimulus/response units connected through a multiplexor to the range of components under test.

Abstract: An Exclusive OR circuit fabricated in CMOS technology is arranged to (1) minimize circuit switching elements and (2) generate inverted inputs within the circuit.

Abstract: An integrated monolithic switch is fabricated in an epitaxial layer united to a semiconductor substrate. The switch includes a Darlington amplifier, a power output switch, a bilateral device, typically a diffused diode, and an epitaxial resistor, the combination being connected between a set of high voltage lines. The epitaxial layer has an appropriate thickness and resistivity to accommodate all active and passive elements. For a first input signal, the switch is connected to one high voltage line. For a second input signal, the switch is connected to the other high voltage line. The switch is adapted to sink current. The diode structure, when forward biased by the sinking current, forms a parasitic path to direct the sinking current to the substrate even though the high voltage lines are up. The Darlington is connected to the switch output to lower output voltage during the sinking condition.A set of switches of the same conductivity type may be employed to drive a cross point in a gas panel display.